Appendix — Federal Trade Trade Commission Commission Commission Commission v. Rambus, Inc. (No. 08-694)

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Supreme Court, U.S.

FILED .

LY an 08-694 NOov24 2008

Ss aes ™

In the Supreme Court of the Anited States

FEDERAL TRADE COMMISSION,

PETITIONER

Vv.

RAMBUS INCORPORATED

ON PETITION FOR A WRIT OF CERTIORARI

TO THE UNITED STATES COURT OF APPEALS

FOR THE DISTRICT OF COLUMBIA CIRCUIT

APPENDIX VOLUME 2 OF 2

WILLIAM BLUMENTHAL

General Counsel

DAVID C. SHONKA

DAVID P. WALES JR. Principal Deputy General

Acting Director Counsel

KENNETH L. GLAZER JOHN F. DALY*

Senior Deputy Director Deputy General Counsel

MELANIE SABO for Litigation

Assistant Director WILLIAM E. COHEN

RICHARD B. DAGEN Deputy General Counsel

SUZANNE MICHEL for Policy Studies

PATRICK J. ROACH LESLIE RICE MELMAN

Attorneys MARK S. HEGEDUS

Bureau of Competition Attorneys

Federal Trade Commission Federal Trade Commission

600 Pennsylvania Avenue NW

Washington, DC 20580

(202) 326-2244

*Counsel of Record

ELLER EEL DEMISE BN EE LEE ELIE BEALE ALD ELE ANC OSI. Fy DD SEDO Sy. BATTERIE

Wicson-EPES PRINTING CO.,INC. — (202) 789-0096 — WASHINGTON, D.C. 20002

387a

APPENDIX G

** PUBLIC VERSION **

UNITED STATES OF AMERICA

FEDERAL TRADE COMMISSION

OFFICE OF ADMINISTRATIVE LAW JUDGES

Docket No. 9302

In the Matter of RAMBUS INC.,

A CORPORATION

INITIAL DECISION

Before: Stephen J. McGuire

Chief Administrative Law Judge

FEDERAL TRAI £ COMMISSION

February 23, 2004

388a

APPEARANCES FOR THE PARTIES

Counsel Supporting Counsel for Respondent:

the Complaint:

M. SEAN ROYALL

GEOFFREY D. OLIVER

PATRICK J. ROACH

GREGORY P. STONE

STEVEN M. PERRY

PETER A. DETRE

SEAN P. GATES

MUNGER, TOLLES & OLSON LLP

355 South Grand Avenue,

35th Floor

Los Angeles. California 90071

A. DOUGLAS MELAMED

KENNETH A. BAMBERGER

WILMER, CUTLER &

PICKERING LLP

2445 M Street, N.W.

Washington, D.C. 20037

Of Counsel:

MALCOM L. CATT

ROBERT P. DAVIS

MICHAEL A. FRANCHAK

THEODORE A. GEBHARD

ANDREW HEIMERT

CHARLOTTE MANNING

LISA D. ROSENTHAL

SARAH E. SCHROEDER

JEROME A. SWINDELL

JOHN C. WEBER

CARY E. ZUK

SEAN C. CUNNINGHAM

JOHN M. GUARAGNA

GARY, CARY, WARE &

FREIDENRICH LLP

401 “B” Street, Suite 2000

San Diego, California 92101

BUREAU OF COMPETITION

FEDERAL TRADE COMMISSION

Washington, D.C. 20580

389a

TABLE OF CONTENTS

PART ONE: INTRODUCTION. ........c:sscessseeeseees 416a"

I. FEDERAL TRADE COMMISS:0N

COMPLAINT .....csccsssessscsssseessessssessseessseen 416a

Il. | RESPONDENT’S ANSWER ........:0:000000-+ A18a

III. ISSUES PRESENTED ..........c.cccccccesseee 419a

IV. PROCEDURAL BACKGROUND........... 420a

V. EVIDENCE........... ei PE eee 421a

VI. SUMMARY OF THE DECISION ............ 423a

PART TWO: FINDINGS OF FACT .........c000000-0 4240

I. DRAM AND THE INVENTIONS OF

DRS. FARMWALD AND HOROWITZ.... 424a

A. DRAM Applications in Computer

RN teense onetaerecie ei eeeee 424a

1, TARR EIEITIOE noc ceccvcesescesevscencecesses 424a

2. The Production of DRAMs............. 426a

a. The DRAM Manufacturing

PN esa eases eee 426a

b. The Various Phases of DRAM

SIOVOTOUIORE ons cvsivescicessiescsesnevee 428a

c. Design Modification During

DRAM Production .................... 430a

B. The Memory Bottleneck Problem ...... 430a

C. Farmwald’s and Horowitz’s Inven-

tions Solve the Memory Bottleneck

* Pagination modified from original to reflect pagination in

Petition Appendix

i].

390a

Problem by Addressing Numerous

BIE Sicoctindl tees Ornaments

Bs SETI FRI os eceainsesciiecrcccensntveves

3. The Memory Interface Protocol ....

RAMBUS: COMPANY DEVELOP-

MENT AND PUBLIC PROMOTION OF

RENE IGE eiccsisvnsiineinpbocisasunsisnavereiaees

A. The Founding of Rambus ...................

1. Securing Venture Capital Fund-

UNE cass acecasamnecasiversonian ase weeneeeeseets

2. Early Business Plan for the

Farmwald/Horowitz Inventions ....

The RDRAM Technology.....................

The 1990 Business Plan .....................

. RDRAM Promotion and Licensing

I dics wincus; actncnnnrnerrss caiman

E. Presentation of the Rambus Inven-

tions to the DRAM Industry ...............

1. Rambus Visits to DRAM

Manufacturers and Systems

RIN scocisciicvessmncennneens

2. Preparation and Description of

the Rambus Inventions Through

Various Technical Publications ....

a. The May 1990 Technical De-

cl iaeasouiaee-oetihinacens

b. The November 1990 Technical

ROTO. sic wssnccanocirctemcsnasasses

434a

436a

437a

438a

439a

442a

443a

445a

448a

449a

45la

39la

c. Siemens Responds With a List

of Questions About Rambus

OD kecseinniwicecitecteptinnen

d. The April 1991 Technical De-

IE iia tincucannerocsxcosdcectoens

. The March 1992 Press Events ...........

. Press Coverage: The March 1992 Mi-

croprocessor Report Article ................

. Rambus’s Disclosure of Inventions

Through Public Documents ................

1. The 1992 Marketing Brochure .....

2. Publications Describing the First

Rambus DIAM .............cccccessessceens

Presentations of the Proprietary

RDRAM Technology and Nondisclo-

SUTO PBT OCRIIG oncsceccns cc cnccecevonasersvenes

. The June 1992 Business Plan .............

. Rambus Patent Applications .............

1. The ‘898 Patent Application .........

es oy 8 nn ee

3. The PCT Application ...............:..--.

4. The ‘898 and PCT Applications

Describe Numerous Inventions ....

a. Description of Access Time

I viscscbeiccsceinnsencincaisninsieiien

b. Description of Block Size .........

Description of Bus Clock ..........

d. Description of Variable Delay

Circuitry With a Feedback

I ex saccientieraiooimnneaamenacns

392a

5. Review of the ‘898 or PCT

Application Should Have Raised

Concerns That Rambus Might Be

Able to Obtain Claims Over the

Four Technologies at Issue ...........

Ill. JEDEC IS A COLLABORATIVE STAN-

DARD SETTING BODY FOR THE

SEMICONDUCTOR INDUSTRY ...........

A. Early History of JEDEC .....................

B. The Purpose and Function of JEDEC

SOPOT SHEESH EEE EH EEEHEEHEEEHEEHEEEEHEEEOEHEETHHETHH HEB EEEEE

C. The Organization of JEDEC ..............

1. Member Companies .......................

2. The JEDEC Council, Board of Di-

rectors and Officers .......................

3. The JC 42 Committee ...................

D. The Standard Development Process ..

E. Rambus’s Involvement in JEDEC .....

SOOO TO HET EH EHH HOE EHHHHEO TES EHEHH ETE HE EHEEEHEH HEHEHE EE EEEEE

2. Rambus Representatives Learn

About the EIA/JEDEC Patent

BUNT ; sivssasnceshdebiNedegpinntavandivstantinconse

3. Rambus Continued to Stay

Abreast of JEDEC and SyncLink

II inci. ccih ol cnnradavetonectdevanhenes

IV. EARLY DEVELOPMENT AND ADOP-

TION OF JEDEC DRAM STANDARDS..

A. The Initial SDRAM Standard ............

1. Demand for a New Generation of

SE eta etni iy ean tenn ace

A4A77va

480a

48la

483a

484a

486a

488a

489a

393a

2. Proposal of a Fully Synchronous

Es scidcaienaichdeniecscetaniuabanchciee ihe 494a

3. Inclusion of Programmable CAS

Latency and Burst Length ............ 498a

4. Presentations of Additional Tech-

IIE “eb xicomeoca ica Teaeeettie rk dcnedaiantaain 503a |

a. Low Voltage Swing Signaling . 503a

b. Dual Bank Design .................... 504a

C. Avute-Precharg®e ..........00c:00sc00000 505a

d. Source Synchronous Clocking . 505a

e. Externally Supplied Reference

EEN. aniccticatebcudiencteniates ss 506a

5. Adoption of the SDRAM Standard

ienaminnebaniaeian cadences anea tn 506a

6. Subsequent Proposals: Costs,

CAS Latency and SDRAM Lite .... 508a

B. DDR SDRAM—The Next Generation

I eis Sane ee es 5lla

1. Work Within and Outside of

I oircc een a setstddicsunacnanns eoraaco ised. 5lla

2. Future Synchronous SDRAM Fea-

I ie harcg eee ee 51l4a

a. Presentation of Programmable

CAS Latency and_ Burst

NE silanssrocternacasuscccentvaueseoeees 515a

b. Discussion of PLL/DLL............. 516a

c. Consideration of Dual Edge

RNIN do tcccinticneneicceicuncensicheess 520a

3. Subsequent Proposed Features .... 523a

394a

a. Externally Supplied Reference

WHE sicvicsecnerictashcmeanerenennann

b. Source Synchronous Clocking .

4. Adoption of the DDR SDRAM

TE escexsicsvinientinmenenaglian

5. Features Incorporated into the

URINE, siscccctecieuceeninanan

me. Cpe Bie fcicrcsenamecue

b. Dual Edge Clocking .................

c. Programmable CAS Latency

and Burst Length .....................

C. Interoperability: The Effect of

JEDEC’s Specifications versus

Manufacturers’ Specifications ............

RAMLINK AND SYNCLINK, THE

SYNCLINK CONSORTIUM, INTEL

AND DRAM MANUFACTURERS ..........

A. The IEEE RamLink and SyncLink

Were SIP seivecicncienineiorcenen

1. The IEEE Membership Require-

ments and Lack of Patent Disclo-

sure Obligations ...............<cs00sseess2-

2. RamLink Was Developed to Stan-

dardize a New Future Memory

TD snuinndincuunneesnaeeee

3. The IEEE SyncLink Project Ema-

nated From and Modified the

Proposed RamLink Standard .......

4. Presentation of the Ram-

Link/Synclink Architecture at

523a

524a

525a

526a

527a

528a

395a

JEDEC—Rambus Elects Not to

Comment On _ Its _ Intellectual

ee Pe

Richard Crisp Indicates That the

SyncLink Proposal May Infringe

Rambus Patents But Declines To

Comment Regarding Rambus In-

tellectual Property ............00.cccc0

Hyundai Negotiates “Other

DRAM” Provision As Part of Its

RDRAM License Agreement .........

B. The SyncLink Consortium .................

Formation and Purpose of the

elke scadeulncedeancbunities

Concern About Patents of Non-

SyncLink’s Activities With Re-

spect to Rambus Patent Applica-

tions and Intel’s Announced Sup-

IE GE TRRMIEEIEE sevscecsevccceccrasseconsesecs

C. Rambus’s Relationships With Intel

and DRAM Manufacturers .................

Rambus Sought Licenses and

Support for RDRAM From DRAM

Manufacturers After Intel En-

dorsed RDRAM Technology ..........

2. Intel and RDRAM Royalty Rates .

Design, Manufacture, and Supply

of Memory Architectures by Mi-

cron and Other DRAM Manufac-

NEN SEER Re EPIRA OE EA OER Ee

529a

530a

533a

534a

536a

537a

540a

543a

396a

Cost Issues Associated With

IIE oricc ca echundetaeupicobusaties 547a

Actions by DRAM Manufacturers 550a

6. The DRAM Industry’s Approach

to Addressing RDRAM Problems.. 559a

7. By 1998 the Rambus-Intel Rela-

tionship Was Deteriorating .......... 560a

8. Technical Problems and Product

Delays With RDRAM...................... 561la

9. Intel’s Announcement That It

Would No Longer Support

RISER SE ne mee bres 562a

ELA/JEDEC PATENT POLICY ............... 564a

A. Good Faith Obligations ...................... 564a

BS. GSTs DERI cccesccccccceresscersssveccsevenes 567a

BD Sica acancpiacensaasdescsenstalomseuiies 569a

iy SE ED dis cvesschacausleh den sevmanpimusre 569a

ET EEE. canudilpincuidelies duaaduolenmviamseineah 570a

3. EIA Legal Guides .......................... 578a

4. EP-3-F and EP-7-A............ccccccseeeres 579a

5. ANSI Patent Policy ........cccccccescesess 581la

D. Committee Forms ...................::00ceeeeees 582a

1. Membership Application ............... 582a

2. Meeting Attendance Roster (Sign-

BU IEE. weicccnncitabeseaseecsénesivencusssnns 582a

3. Committee Ballots ......................... 585a

4. Members’ Manual .......................... 586a

5. Patent Tracking List ..................... 588a

397a

E. Contemporaneous Correspondence .... 589a

1. The McGhee Memorandum .......... 589a

2. Correspondence Regarding the

Dell Consent Agreement................ 590a

3. Correspondence Regarding Mi-

cTON Disclosure ..............ccccccsesesseees 592a

F. Conduct of Parties in JEDEC ............. 594a

a: CII eiviceecietecattnenabslascubaiuas 594a

Z. WANG LAtigatiON .....cccccvesccesercsceess 595a

3. IBM’s Patent Position ................... 595a

4. Hewlett Packard’s Patent Posi-

SINE casancnceesaenesnseibencienmanseebaxntiniandee 597a

5. Texas Instruments’ QUAD CAS

SUID -ccvenscuuenntienesnnesnsanmendensenbaniaiientia 598a

6. Micron’s Presentation on Burst

SIE Psussisnadiitaadaedcudaecdedthiadasmucdamadmsesiads 600a

7. Hyundai and Mitsubishi’s Presen-

tation on SLDRAM ......................... 60la

ike ENN III cs ccaicscccaseususceesansusecsonvas 603a

1. A Policy in Transition ................... 603a

2. Creation of Ambiguity and Confu-

sion Regarding the Policy .............. 603a

3. Unsuccessful Efforts to Expand

the Patent Policy ......0..ccccscssceeteceses 605a

4. Changes in Policy Language ......... 610a

a. EIA Patent Policy .................... 610a

b. Changes Found in JEP 21-I .... 6lla

5. Conflicts in the Trial Testimony ... 613a

398a

a. Trial Testimony Conflicts Re-

garding Whether the Patent

Policy Applied to Patent Ap-

plications and Intentions to

File Patent Applications ..........

b. Trial Testimony Conflicts Re-

garding Whether Members

Should Disclose Actual Claims

or Whether a Patent Number

WUE CIEE vives sxecnnesssverecnesices

c. Trial Testimony Conflicts Re-

garding Whether More Than

Essential Patents Were In-

cluded in the Policy ..................

d. Trial Testimony Conflicts Re-

garding the Timing of Disclo-

I eecrireteniuanciaeinnccumidecteavieieiasenns

| _ ERTOIREERRR Rene Peter rl eer oat en a

. Disclosures Were Encouraged and

TN ok cdsdssevivenenvctunbacianetecwxains

. Patent Applications or Intentions

To File Patent Applications Were

Not Covered by the Policy .............

. Members Were Encouraged To

Disclose Patents That Were Es-

sential To Practice the Standard ..

. There Was No Duty To Search for

Intellectual Property Issues .........

. The Policy was Limited To

Participants With Actual Knowl-

NINN cock conta tucdixanevetevebieier canseets

6l4a

615a

617a

618a

620a

621a

622a

623a

VII.

399a

6. The Patent Policy Did Not Apply

After a Company Withdrew From

EE sciuiniskivsetianiinminneeenannesn

7. If Disclosure Was Made, It Was

Encouraged No Later Than the

TERE OF TIRE «00 06scccseesevssssseves

JEDEC 42.3 COMMITTEE MEMBERS

WERE NOT MISLED BY RAMBUS ON

ISSUES RELATING TO RAMBUS IN-

TELLECTUAL PROPERTY ....................

A. JEDEC Committee Leaders and

Members Were Fully Aware of Ram-

bus’s Patents With Respect To Fea-

tures Being Considered for Incorpo-

ration into JEDEC Standards ............

1. Crisp Did Not Mislead JEDEC At

the May 1992 Committee Meeting

Regarding Rambus’s Intent To

Seek Patent Rights Over Certain

APE WONT one ccccecsncncvecsseersss

a. IBM and Siemens ...................

b. The May 1992 JC 42.3 Meet-

Se iiilidatoindiiicendiniciuenintiannsncnet

C. Fe PIII dec diciccscccceeccsenes

d. After the May 1992 JC-42.3

I orice eee

2. PCT Application Discussed At the

September 1993 Meeting ...............

3. The May 1995 JC 42.3 Meeting ....

4. The September 1995 JC 42.3

| AER RR eS oo ORR IT

625a

626a

Vfl.

400a

5. Rambus Met With Manufacturers

NE I sivicccccsetenineprncernsers

6. JEDEC Members Viewed Ram-

bus’s Patents As a Collection of

IED Sedecsiacs te cokecdauaeteccunnauate.

The Deli Consent Order and Ram-

bus’s Last JEDEC § Meeting—

December 1995 To January 1996 ......

Ongoing Discussions of Rambus Pat-

ents by JEDEC Members After June

DE dibssthsbidetiaaaiaenesinntmelnanebetie

RAMBUS WAS NOT IN /IOLATION

OF ANY JEDEC RULES ...........00000.00...

Rambus Was Not in Violation of the

JEDEC Patent Policy .........................

There Is No Evidence that Crisp,

During the Time Rambus Partici-

pated in JEDEC, Had Actual Knowl-

edge that Rambus Had Claims that

Could Be Asserted Against JEDEC-

Compliant SDRAM or DDR SDRAM

IEE vadcecytsnccnunteedeceiadesodeunetastecenes

. Rambus Did Not Misappropriate In-

formation From JEDEC .....................

. There Were No Prohibitions Which

Precluded Rambus From Seeking

Patent Protection For Inventions

that Related to JEDEC Standards ...

Rambus Followed the Advice of Its

Legal Counsel in Determining Its

Legal Obligations to JEDEC ..............

644a

647a

649a

655a

659a

662a

40la

F. During the Time of Its Participation

in JEDEC Rambus Had No Intellec-

tual

Property Interests That It

Would Have Been Required To Dis-

close Even If Disclosure Was Manda-

tory

SPORE EEE EEE EEE ETHER EERE EEE HEHE EEE HEHEHE EEE EEEE

1. Rambus Had No Patents That It

Was Required To Disclose .............

The ‘327 Patent Contains

Various Limitations .................

Rambus Had No Duty To Dis-

close the ‘327 Patent Based On

the Hardell Presentation..........

Rambus Had No Duty To Dis-

close the ‘327 Patent Based On

the Survey Ballot .....................

Rambus Had No Duty To Dis-

close the ‘327 Patent Based On

the Samsung Presentation ......

Complaint Counsel Did Not

Provide Sufficient Evidence to

Determine Whether the Pres-

entations Would Trigger the

Pete PORES daccciescconsencmnen

2. Rambus Had No Undisclosed Pat-

ent Applications That It Was Re-

quired to Disclose, Even if the

Policy Required Disclosure ...........

G. Rambus Withdrew From JEDEC Be-

fore Forma! Work On the Standardi-

zation of the DDR SDRAM Began ......

H. Document Destruction by Rambus ....

664a

666a

667a

668a

669a

672a

676a

402a

RAMBUS HAS MONOPOLY POWER

IN THE RELEVANT MARKETS ............

Bi. PHRPOVORE MEGrets ............00scssesesecessvess

Re BEE INES 5-5. cevcveveseesecoess

2. Geographic Market ....................00

See RE FONNNT 0... neccsdecnessocennes

BR IG CEIINI oaeceeescveccavonsevercvecses

2. Assertion of Patents ...........0.0........

3. JEDEC Standardization ...............

a. Rambus’s Market Power Is

Not Attributable to the Inclu-

sion of Its Technology In

JEDEC Standards ...............-.-..

b. Rational Manufacturers and a

Rational Standard Setting Or-

ganization Would Have Still

Adopted the Rambus Tech-

nologies Had Disclosure Oc-

EE hits Haswlineneacheaaneneeees

c. Intel’s Choice of RDRAM Con-

ferred Market Power, Not

JEDEC Standardization ..........

THE CHALLENGED CONDUCT WAS

POPE BLA ICIINAIR © 2250 s000seoesn-connseeser

A. Rambus Had a Legitimate Business

Justification For Not Disclosing its

Proprietary Patent Information .........

B. Rambus’s Conduct Did Not Impact

Equal or Superior Alternatives ..........

682a

683a

684a

685a

687a

693a

694a

697a

403a

C. The “Commercial Viability” Analysis

of Complaint Counsel’s Economic

ING iccsihcicinntceaeenee

D. The Assumption by Complaint Coun-

sel’s Economic Expert that Rambus

Knowingly Assumed the Risk Of

Losing Its Ability To Enforce Its Pat-

E. The Assumption by Complaint Coun-

sel’s Economic Expert That Rambus

Violated a JEDEC Rule or Made

Misrepresentations to JEDEC ...........

F. The Economic Evidence Regarding

“Hold Up” and Disclosure Costs .........

THE EVIDENCE DOES NOT SUP-

PORT COMPLAINT COUNSEL’S AR-

GUMENT THAT THERE WERE VI-

ABLE ALTERNATIVES TO RAMBUS’S

FTAA on dew ciecnesesinnpninctecaxsnsesaeess

A. The Testimony of Professor Jacob Re-

garding Allegedly Viable Alterna-

tives Is Not Persuasive .......................

B. Complaint Counsel Did Not Prove

That There Were Viable Alternatives

to the Rambus Technologies Adopted

Heth SRE NOE sieickceiaciecdvcnvetccccruees

1. Programmable CAS Latency ........

a. Complaint Counsel Did Not

Prove That the Use of Fixed

CAS Latency Parts Was a Vi-

able Alternative .............0.....062.

706a

710a

J71lla

713a

715a

717a

404a

Complaint Counsel Did Not

Prove That Programming CAS

Latency with Fuses Was a Vi-

able Alternative ............ceee

Complaint Counsel Did Not

Prove That Scaling CAS La-

tency With Clock Frequency

Was a Viable Alternative ........

Complaint Counsel Did Not

Prove That Using Dedicated

Pins to Identify the Latency

Was a Viable Alternative ........

Complaint Counsel Did Not

Prove That Identifying CAS

Latency in the Read Command

Was a Viable Alternative ........

Complaint Counsel Did Not

Prove That Staying with

Asynchronous Technology Was

a Viable Alternative .................

2. Programmable Burst Length ........

Complaint Counsel Did Not

Prove That the Use of Fixed

Burst Length Parts Was a Vi-

able Alternative ..................0006

Complaint Counsel Did Not

Prove That Programming

Burst Length With Fuses Was

a Viable Alternative .................

Complaint Counsel Did Not

Prove That Using Dedicated

Pins To Identify Burst Length

Was a Viable Alternative ........

725a

728a

73la

734a

736a

738a

739a

743a

405a

Complaint Counsel Did Not

Prove That Explicitly Identi-

fying Burst Length in the

Read Command wa a Viable

FN ee

Complaint Counsel Did Not

Prove That Using a _ Burst

Terminate Command Was a

Viable Alternative ..............00....

Complaint Counsel Did Not

Prove That Using CAS Pulse

To Control Data Output Was a

Viable Alternative ........0......00...

3. Given the Cost Performance

Differences, an Economically Ra-

tional DRAM Manufacturer

Would Have Adopted and. Li-

censed the Rambus Technologies

Incorporated In SDRAM If It Had

Known Of Rambus’s_ Royalty

RAR BM AVRO nncccececscccescecsecsese:

C. Complaint Counsel Did Not Prove

That There Were Viable Alternatives

To the Specified Rambus Technolo-

gies Adopted In DDR SDRAM ...........

1. Dual-Edge Clocking ......................

Complaint Counsel Did Not

Prove That Interleaving On-

Chip Banks Was a Viable Al-

I ii cata

Complaint Counsel Did Not

Prove That Interleaving On-

747a

7T47a

750a

75la

757a

758a

406a

Module Ranks Was a Viable

PII ov cies sc sevvexsxdneoxeresasss 76la

ec. Complaint Counsel Did Not

Prove That Increasing the

Number of Pins on the DRAM

Was a Viable Alternative ........ 764a

d. Complaint Counsel Did Not

Prove That Increasing the

Number of Pins on the Module

Was a Viable Alternative ........ 767a

e. Complaint Counsel Did Not

Prove That Doubling the Clock

Frequency Was a Viable Al-

NE oes itenaieeiare 767a

f. Complaint Counsel Did Not

Prove That Using Simultane-

ous Bi-directiona] I/O Drivers

Was a Viable Alternative ........ 771a

g. Complaint Counsel Did Not

Prove That Using Toggle Mode

Was a Viable Alternative ........ 773a

Be ENS So ticcrdencericriinedniens 774a

a. Complaint Counsel Did Not

Prove That Putting a DLL On

the Memory Controller Was a

Viable Alternative..................... 776a

b. Complaint Counsel Did Not

Prove That Putting a DLL On

the Module Was a Viable Al-

ph cuties skcebeneinesanuden T77a

c. Complaint Counsel Did Not

Prove That Using a Vernier

407a

Method To Account For Skew

Was a Viable Alternative ........ 7179a

d. Complaint Counsel Did Not

Prove That Increasing the

Number of Pins on the DRAM

Was a Viable Alternative ........ 781a

e. Complaint Counsel Did Not

Prove That Relying on the

DQS Data Strobe Was a Viable

PIROPIIID osisscicsenciecvecrsedinccsseeee 781la

f. Complaint Counsel Did Not

Prove That Read Clocks Were

a Viable Alternative ................. 782a

3. Given the Cost-Performance

Differences, Economically Ra-

tional DRAM Manufacturers

Would Have Adopted and Li-

censed the Rambus Technologies

Incorporated in DDR and SDRAM

sosiinausaias te tciplabebelcan edhe idles 783a

EVEN ASSUMING THAT ALTERNA-

TIVES DID EXIST, JEDEC WOULD

NOT HAVE REJECTED THE RAMBUS

FEE IRI voancessnkssctpinereceivindenidconns 787a

A. Whether JEDEC Would’ Have

Adopted Alternatives To Rambus’s

SDRAM and DDR Technologies Had

Rambus Made Additional Disclosures 787a

B. JEDEC Might Not Have Sought a

RAND Assurance From Rambus

Even if Rambus Had Made Disclo-

408a

C. If JEDEC Had Sought a RAND

Assurance, It Would Still Have

Adopted Rambus’s Technologies ........

1. Rambus Would Have Given a

RAND ARGUPATICE osccccicceccsissesevescees

2. It is Unlikely There Would Have

Been Any Ex Ante Negotiations ....

3. JEDEC Would Have Adopted

Rambus’s’~ Technologies with

Rambus’s RAND Assurance .........

XIII ANALYSIS OF THE BUT/FOR WORLD

SET PORES esnivepsnceinninx eaten

A. The Revealed Preference Theory —

JEDEC Continued To Select Rambus

Technologies Even While Rambus

Was Asserting Its Patent Rights .......

1. Proposed Alternatives Not

Adopted By JEDEC ....................06.

Alternative To On-Chip PLL

ite SORPONE bi stirisinseereernrcess

JEDEC Selection of Program-

mable CAS Latency .................

JEDEC Selection of Program-

mable Burst Length .................

JEDEC Selection of Dual-Edge

CN oi ss acsicctocceommnne

2. JEDEC Continued to View Ram-

bus Patents As A Collection Of

PP FA on cencevescasan caus

XIV. RAMBUS’S ROYALTY RATES ARE IN

FACT REASONABLE AND NONDIS-

CARER ININ CSIP edsdselvcormpnseescinconimarenen

796a

802a

806a

812a

815a

816a

817a

818a

819a

820a

409a

A. Rambus’s Royalty Rates Are Reason-

EMRE cash ace saiencaputieecubetepuonebasiien

1. The JEDEC Rules Defined “Rea-

sonable” as the Rate Determined

I UT... scvennesecursienanereess

Rambus’s Royalties Are Compara-

ble To Other Licensing Rates in

the Industry and Are “Reason-

able” Under the JEDEC Rules .....

_ B. Rambus’s Royalty Rates Are Nondis-

RSE Re eRe ne ee

JEDEC Has Left the Definition of

“Nondiscriminatory” to the Mar-

ket and the Courts ....................008

2. The Economic Evidence That

Rambus’s’_ Royalty Rates Are

Nondiscriminatory ................:ceeee

XV. THE EVIDENCE DOES NOT ESTAB-

LISH THAT THE DRAM INDUSTRY IS

LOCKED IN TO USING THE RAMBUS

pe Se Fe co) ae

A. An Historical Look at How the

DRAM Industry Transitions To New

IE cd sce vaicdivecevexeeinns nice eeenceoes

Statistical Evidence of Co-Exist-

ing DRAM Standards ....................

Industry Redesign of DRAM..........

The Manufacture of Multiple

DRAMs to Accommodate New

PI cos iaxesaiesencacavevcconnbavncestta

Coordination of New Industry

NI Ce din ii cost bs Cnvuxiunsiasacereanes

826a

827a

833a

835a

837a

410a

B. Switching Costs Do Not Support The-

ory of Industry Lock In.....................0..

1. Such Costs Are Not Prohibitive ....

2. Coordination Issues Would Not

Preclude Switching to New Tech-

PART THREE: ANALYSIS AND CONCLU-

II.

IIT.

Wi actnettvnicnciuannendneacentins

PROCEDURAL ISSUES ...........ccccsccecseees

Bi. CRI GE Fi cnkececccsscciccssestscscsseres

B. The Adverse Presumpti ns Are Not

Material to the Disposition of the

1. The First and Second Adverse

Presumptions Are Moot .................

2. The Five Remaining Adverse Pre-

sumptions Are Not Relevant to

Any Material Issues ......................

3. A “Missing Witness” Inference Is

DONE FI sniscciessssetcrerercccins

C. The Infineon Litigation .......................

ED, UM irc acecnkccucccdecusuciactasvesecees

A. Possession of Monopoly Power in the

Relevant Markets. ...............cceccseseceeeees

1. Relevant Markets ..........................

a. Geographic Market ..................

849a

4ila

b. Product Markets. ..................008

Monopoly Power .................::ssseceeee

B. No Pattern of Anticompetitive Acts

SE I sciiensaitenniacbainaecsecies

The Legal Theory Upon Which

Complaint Counsel Challenge Re-

spondent’s Conduct Lacks a Rea-

sonable Basis in Law ....................

The Duties Upon Which Com-

plaint Counsel Base Their Chal-

lenge Must Be Clear....................00.

The Evidence Presented at Trial

Does Not Provide a Factual Basis

for Finding a Pattern of Anticom-

petitive Acts and Practices ...........

a. No Duty to Disclose

Intellectual Property Based on

GI EN Abstsoorchionasnnce

b. No Duty to Disclose Intellec-

tual Property Based on Open

EE icici aonteeea

c. No Duty to Disclose Intellec-

tual Property Based on the

EIA/JEDEC Patent Policy .......

i. Disclosure of Intellectual

Property Under the

EIA/JJEDEC Patent Policy

Was Voluntary .................04.

ii. The EIA/JEDEC Patent

Policy Was Limited to Is-

sued Patents, Not to Patent

873a

879a

88la

882a

883a

885a

888a

412a

Applications or Intentions

SE sircocccetecindibatevctendtisieans 893a

ii. The EIA/JEDEC Patent

Policy Applied to Essential

RRNA aOR 894a

iv. The EIA/JJEDEC Patent

Policy Was Triggered at the

Time of Submitting Com-

TICES TIBIINN oes ccccesctecsseess 896a

d. The Unsuccessful Attempt to Ex-

pand the EIA/JEDEC Patent

Policy Created Ambiguity and

a aor rea wecalesienpenes 897a

e. Rambus Had No Patents or

Pending Patents That Would

Have Been Required to be Dis-

closed by the ELA/JEDEC Pat-

NN ceicssapnsnniinebcisnieotocconess 899a

ee aii cchainaisinreseunennees 900a

BR. EREP PRONG . osc cscescorsessoees 904a

4. The Evidence Presented at Trial

Does Not Provide a Factual Basis

for Finding That Rambus Made

Affirmative, Misleading State-

ee Le) Sk 906a

5. Amendments to Claims __ to

Broaden Patent Applications

Were Not Improper .......................- 910a

C. No Exclusionary Conduct ................... 915a

1. Exclusionary Conduct Defined ..... 91l5a

2. Legitimate Business’ Justifica-

ee rare a ceuacincneans 917a

41l3a

3. Conduct Before Standard Setting

Organizations ............... centile. 919a

4. Violations of Extrinsic Duties or

Deception Affecting Consumers

Not Exclusionary Conduct ............ 923a

D. No Intent .................. eecad hiaiaawan yeni eemees 928a

PN eee en 928a

2. Complaint Counsel Have Not

Demonstrated That Respondent

Intended to Mislead or Deceive

SARA RA -OrU 930a

3. No Inference of Intent ................... 933a

4. Other Factors Demonstrating

That The Intent Element Is Not

re ee ee 934a

a la 935a

ee eS ae 935a

2. No Causal Link Between JEDEC

Standardization and _ Respon-

dent’s Acquisition of Monopoly

NI Miata lnnicadincaas sc osavaiveaeenseancdiunnes 937a

a. Rambus Did Not Acquire Mo-

nopoly Power by Virtue of

JEDEC’s Standard Setting ...... 937a

b. Rambus Acquired Monopoly

Power as a Result of its Supe

rior Technology and _ Intel’s

Choice of its Technology .......... 939a

3. No Reasonable’ Reliance by

"Ie ne ea nh or REN ee 940a

4l4a

F. No Anticompetitive Effects ................. 949a

1 Anticompetitive Effects Defined ... 949a

2. Complaint Counsel Have Not

Demonstrated That There Were

Viable Alternatives to Rambus

POI sicnceccicsnicnseniamieeversesviws 951la

a. Programmable CAS Latency ... 953a

b. Programmable Burst Length .. 953a

ce. Dual-edge Clocking .................. 954a

GC, Cs TEs a cesienescccversvcaveicnes 955a

3. Analysis of the Economic Evi-

ieee 956a

a. The Methodology Used _ by

Complaint Counsel’s Economic

Expert Is Flawed ...................... 956a

b. In the ‘“But/For” World,

JEDEC Would Not Have Re-

jected the Rambus Technolo-

gies Even if Alternatives Did

Exist and Rambus Had Made

the Additional] Disclosures ...... 960a

c. JEDEC’s “Revealed Prefer-

ence” For Rambus’s Technolo-

OE icccnsetsnvabiell ottenen-an ieswenenineciens 964a

4. Complaint Counsel Have Not

Demonstrated That Rambus’s

Conduct Resulted in Higher

Prices to Coneuinsers «......5..00.0cresse. 966a

a. Rambus’s Royalty Rates Are

I i nog Gite an ales 967a

4l5a

b. Rambus’s Royalty Rates Are

Nondiscriminatory ...............2.. 969a

G. JEDEC Is Not Locked In .................... 970a

IV SUMMARY OF LIABILITY ..................... 973a

PART FOUR: SUN. MARY OF CONCLUSIONS

I LR ivicisscncnsnsivueeenncicstiaetiednae 974a

416a

IN THE MATTER OF RAMBUS INCORPORATED

Docket 9302; File No. 0110017

Initial Decision, February 24, 2004

INITIAL DECISION

Before: Stephen J. McGuire, Chief Administrative

Law Judge

PART ONE: INTRODUCTION

This Initia] Decision is divided into four parts. Part

One is the introduction, which includes a summary of

the allegations contained in the Complaint; the

defenses asserted in Respondent’s Answer; the issues

presented; the procedural background; a comment on

the evidence; and a summary of the decision. Part

Two contains the separately numbered findings of

fact. Part Three contains the analysis and conclu

sions of law, which provides an overview of the legal

theories asserted by Complaint Counsel; sets forth

the applicable law on each of the elements necessary

to find a violation; and then applies the law to the

facts established at trial. Part Four contains the

summary of the conclusions of law and the Order of

the Court.

I FEDERAL TRADE COMMISSION

COMPLAINT

The Federal Trade Commission (“FTC”) issued its

Complaint in this matter on June 18, 2002. The

Complaint charges that Respondent, Rambus Inc., a

corporation, violated Section 5 of the Federal Trade

Commission Act (“FTC Act”), as amended. 15 U.S.C.

§ 45.

417a

The Complaint charges Respondent with three vio-

lations. The first violation charges that Respondent

engaged in a pattern of anticompetitive and ex-

clusionary acts and practices, whereby it obtained

monopoly power in the synchronous DRAM technol-

ogy market and narrower markets encompassed

therein, in violation of Section 5 of the FTC Act.

(Complaint J 122). The second violation charges that

Respondent engaged in a pattern of anticompetitive

and exclusionary acts and practices with a specific

intent to monopolize the synchronous DRAM techno!-

ogy market and narrower markets encompassed

therein, resulting, at a minimum, in a dangerous

probability of monopolization in each of the markets,

in violation of Section 5 of the FTC Act. (Complaint

{ 123). The third violation charges that Respondent

engaged in a pattern of anticompetitive and exclu-

sionary acts and practices, whereby it unreasonably

restrained trade in the synchronous DRAM technol-

ogy market and narrower markets encompassed

therein, which acts and practices constitute unfair

methods of competition in violation of Section 5 of the

FTC Act. (Complaint J 124).

The Complaint alleges that Respondent partici-

pated in the work of the JEDEC Solid State Tech-

nology Association (“JEDEC”), an industry standard

setting organization in which Respondent was a reg-

ular participant, without making it known to JEDEC

or to its members that Respondent sought to ob-

tain patents on technologies adopted in the relevant

JEDEC standards. (Complaint {7 2, 43, 44, 45, 46).

Respondent’s alleged scheme further entailed perfect-

ing its patent mghts over these same technologies

and then, once the standards had become widely

adopted within the DRAM industry, enforcing such

patents worldwide against companies manufacturing

418a

memory products in compliance with the JEDEC

standards. (Complaint {J 2, 43, 44, 45, 46).

Respondent is alleged to have concealed informa-

tion in violation of JEDEC’s operating rules and

procedures which Complaint Counsel argue imposed

upon JEDEC members an obligation to “disclose any

patents, or pending patent applications, involving

the standard-setting work.” (Complaint {J 20, 21, 24,

79). In addition, the Complaint alleges a “basic rule”

of JEDEC to avoid anticompetitive activity and a

commitment to avoid, where possible, incorporation

of patented technologies. (Complaint {If 17, 18, 19,

20, 22). The Complaint alleges that Respondent

violated these duties by conveying to JEDEC the

materially false and misleading impression that it

possessed no relevant intellectual property mghts.

(Complaint {{ 2, 80).

The Complaint further alleges that Respondent’s

conduct caused anticompetitive effects including in-

creased royalties, increase in the price of synchronous

DRAM and products incorporating synchronous

DRAM, decreased incentives to produce memory

using synchronous DRAM technology, and harms to

standard setting organizations and activities. (Com-

plaint 79 119, 120).

il. RESPONDENT’S ANSWER

In its Answer filed on July 29, 2002, Respondent

alleged as an affirmative defense that the Complaint

failed to state a claim under Section 5 of the FTC Act.

The Answer denied the material allegations of the

Complaint and asserted that the evidence would

show that JEDEC’s rules and policies did not impose,

and were not commonly understood to impose, the

419a

disclosure obligations set out in the Complaint.

(Answer, pp. 1-2).

Respondent asserted in its Answer that the

evidence would show that it did not have, until after

it left JEDEC, any undisclosed patents or patent

applications that contained claims reading on de-

vices manufactured in accordance with any JEDEC

standard. (Answer, p. 2). Respondent also asserted in

its Answer that the evidence would show that

JEDEC did not rely on any purported silence on

Respondent’s part at JEDEC meetings and instead

chose to adopt certain technologies because of the

cost/performance advantages of those technologies

and the absence of reasonable alternatives. (Answer,

p. 2).

Respondent’s Answer asserted that in light of the

absence of a duty to disclose, in light of the absence of

pending claims reading on JEDEC standards, and in

light of the other evidence to be considered at trial, it

would be clear that Respondent’s alleged failure to

disclose its potential intellectual property claims had

no anticompetitive effect in any market and that

Respondent had not violated Section 5. (Answer, pp.

1-3).

Ill. ISSUES PRESENTED

The issues presented in this case are:

(1) whether Respondent engaged in a pattern

of deceptive, exclusionary conduct by subverting

an open standards process;

(2) whether Respondent utilized such conduct

to capture a monopoly in technology-related

markets;

420a

(3) whether Respondent’s challenged conduct

violated principles of antitrust law; and

(4) whether Respondent’s conduct resulted in

anticompetitive injury.

IV. PROCEDURAL BACKGROUND

On June 18, 2002, the Commission issued its

Complaint. This case was initially assigned to Ad-

ministrative Law Judge (“ALJ”) James P. Timony.

Rambus filed a motion to stay the proceeding until

the Federal Circuit issued its decision in Rambus Inc.

v. Infineon Technologies, an appeal of a jury verdict

against Rambus. The Federal Circuit reversed the

jury verdict of fraud and remanded the case, as

discussed more fully in Part III, Section I.C. An

Order Denying Motion for Stay was issued in this

case on July 18, 2002. On July 29, 2002, Rambus filed

its Answer in this matter.

On February 26, 2003, ALJ Timony issued an

Order On Complaint Counsel’s Motions For Default

Judgment and For Oral Argument which imposed

seven rebuttable presumptions against Rambus

based on a finding of intentional destruction of evi-

dence. This Order is discussed in Part III, Section

I.B.

On February 28, 2003, ALJ Timony retired from

federal service. Stephen J. McGuire was _ subse-

quently appointed FTC Chief Administrative Law

Judge and assigned the Rambus matter.

Trial in this proceeding commenced on April 30,

2003. The 54 day administrative hearing produced a

voluminous evidentiary record including 44 live wit-

nesses, 1,770 admitted exhibits, nearly 12,000 pages

of trial transcript, and hundreds of pages of depo-

42la

sition transcripts. The last day on which testimony

was received was August 1, 2003. The parties then

filed Post-Trial Briefs, Proposed Findings of Fact,

and Conclusions of Law, and replies thereto. Closing

arguments and oral examination by the Court was

conducted on October 8, 2003. Following the closing

arguments, the hearing record was closed pursuant

to Commission Rule 3.44(c), by Order dated October

9, 2003. Due to the exceptional circumstances of the

complexity of the issues presented, the volumes of

evidence introduced at trial, and review of the com-

prehensive proposed findings of fact and post-hearing

briefs, it was necessary to extend the deadline for

filing the Initial Decision within one year of the

issuance of the Complaint. By Order dated December

23, 2003, the Commission also extended the time for

filing the Initial Decision within 90 days of the close

of the hearing record until February 17, 2004.

V. EVIDENCE

The Initial Decision is based on the transcript of

the testimony, the exhibits properly admitted in

evidence, and the proposed findings of fact, briefs,

conclusions of law, and replies thereto filed by the

parties. Once a finding of fact is established, it is

cited to in subsequent sections or in the analysis by

the designation “F.”’

' This opinion uses the following abbreviations for citations:

Comp. - Complaint

F. - Finding of fact

CX - Complaint Counsel Exhibit

RX - Respondent Exhibit

JX - Joint Exhibit

422a

The parties submitted extensive post-trial briefs

and reply briefs. The Initial Decision addresses only

material issues of fact and law. Proposed findings of

fact not included in the Initial Decision were rejected,

either because they were not supported by the

evidence or because they were not dispositive to the

determination of the allegations contained in the

Complaint. The Commission has held that Admin-

istrative Law Judges are not required to discuss the

testimony of each witness or all exhibits that are

presented during the administrative adjudication. Jn

re Amrep Corp., 102 F.T.C. 1362, 1670 (1983). Fur-

ther, administrative adjudicators are “not required to

make subordinate findings on every collateral con-

tention advanced, but only upon those issues of fact,

law, or discretion which are ‘material.” Minneapolis

& St. Louis Ry. Co. v. United States, 361 U.S. 173,

193-94 (1959).

Many of the documents and parts of the oral

testimony were received into the record in camera.

Where an entire document or where certain trial

testimony was given in camera treatment for trial,

but the portion of the document or the trial testimony

utilized in this Initial Decision does not rise to the

level necessary for in camera treatment, such infor-

Tr. - Transcript of Testimony before the Administrative

Law Judge

Dep. - Transcript of Deposition

Stip. - Stipulation

CCPFF - Complaint Counsel’s Proposed Findings of Fact

CCPHB - Complaint Counsel’s Post-Hearing Brief

CCPHRB - Complaint Counsel’s Post-Hearing Reply Brief

RPHB - Respondent’s Post-Hearing Brief

RPHRB - Respondent's Post-Hearing Reply Brief

423a

mation is disclosed in the public version of this Initial

Decision, pursuant to Commission Rule 3:45(a) (the

ALJ “may disclose such in camera material to the

extent necessary for the proper disposition of the

proceeding”). In accordance with 16 C.F.R. § 3.45(f),

material that has been given in camera treatment is

indicated in bold font and braces in the in camera

version. Where in camera material had been redacted

from the public version of the Initial Decision, braces

precede the redacted material.

VI. SUMMARY OF THE DECISION

Complaint Counsel have failed to sustain their

burden of proof with respect al] three of the violations

alleged in the Complaint. First, the evidence at trial

establishes that Complaint Counsel failed to prove

the facts they alleged in the Complaint. Second, an

analysis of the legal theories advanced by Complaint

Counsel demonstrates that there is no legal basis for

finding a violation of Section 5 of the Federal Trade

Commission Act, either as based on other antitrust

laws or solely as an unfair method of competition.

Third, an application of the facts established at trial

to the legal theories asserted leads to the conclusion

that Complaint Counsel have failed to prove their

case.

The evidentiary record demonstrates that: (1) the

EIA/JEDEC patent policy encouraged the early, vol-

untary disclosure of essential patents and Respon-

dent did not violate this policy; (2) the case law upon

which Complaint Counsel rely to impose antitrust

liability is clearly distinguishable on the facts of this

case; (3) Respondent’s conduct did not amount to

deception and did not violate any “extrinsic duties,”

such as a duty of good faith to disclose relevant

patent information; (4) Respondent did not have any

424a

undisclosed patents or patent applications during the

time that it was a JEDEC member that it was

obligated to disclose; (5) amendments to broaden

Respondent’s patent applications while a member of

JEDEC were not improper, either as a matter of law

or fact; (6) by having a legitimate business justi-

fication for its actions, Respondent did not engage in

exclusionary conduct; (7) Respondent did not inten-

tionally mislead JEDEC by knowingly violating a

JEDEC disclosure rule; (8) there is no causal link

between JEDEC standardization and Respondent's

acquisition of monopoly power; (9) members of

JEDEC did not rely on any alleged omission or

misrepresentation by Respondent and, if they had,

such reliance would not have been reasonable; (10)

the challenged conduct did not result in anticom-

petitive effects, as Complaint Counsel did not

demonstrate that there were viable alternatives to

Respondent’s superior technologies; (11) the chal-

lenged conduct did not result in anticompetitive ef-

fects as the challenged conduct did not result in

higher prices to consumers; and (12) JEDEC is not

locked in to using Respondent’s technologies in its

current standardization efforts.

For these reasons, Complaint Counsel have failed

to sustain their burden to establish liability for

the violations alleged. Accordingly, the Complaint is

DISMISSED.

PART TWO: FINDINGS OF FACT

I. DRAM AND THE INVENTIONS OF DRS.

FARMWALD AND HOROWITZ

A. DRAM _ Applications in Computer

Systems

1. DRAM Defined

reenter

425a

1. DRAM stands for “dynamic random ac-

cess memory.” (Rhoden, Tr. 266). DRAM is a

type of electronic memory. (Rhoden, Tr. 266).

DRAM is “dynamic” because it needs to be

refreshed every fraction of a second. (Rhoden,

Tr. 266-67).

2. The primary use for DRAM is in com-

puter systems. (Rhoden, Tr. 267-68; Gross, Tr.

2272-73).

3. DRAMs are also used in a wide range of

other products involving computer systems.

(Sussman, Tr. 1362). These products include

printers, PDAs (personal digital assistants),

and cameras. (Kellogg, Tr. 4986-87; Tabrizi,

Tr. 9126-27; Krashinsky, Tr. 2770-71; Farm-

wald, Tr. 8206-07; Gross, Tr. 2272-73).

4. Typically, multiple DRAM chips are

placed on a memory module, which is a small

printed circuit board. (Rhoden, Tr. 272-73).

The module containing the DRAM chips

connects to a motherboard. (Rhoden, Tr. 270,

273). In some applications, such as graphics

cards, the DRAM chips are not put in memory

modules. (Wagner, Tr. 3871-72).

5. A DRAM is made up of a number of cells.

(Rhoden, Tr. 359). Information is stored in the

cell capacitor as either a high or low voltage.

(Rhoden, Tr. 359). The cells of the DRAM are

divided into an array via a series of rows and

columns with the cells located at the

intersections of those rows and columns.

(Rhoden, Tr. 359-60). Access to the cell

capacitor is made by activating a transistor,

which transfers the voltage in the capacitor to

426a

a column, also known as a bit line. (Rhoden,

Tr. 359-60).

6. In order for a DRAM to have any value, it

must be compatible and interoperable with the

other components in the same specific system

that include the DRAM. (Peisl, Tr. 4410; CX

1075 at 1; Heye, Tr. 3655-65; Jacob, Tr. 5562-

66).

2. The Production of DRAMs

a. The DRAM Manufacturing Process

7. The starting point in the manufacturing

process is a bare silicon wafer. (Becker, Tr.

1116-17).

8. During the course of the manufacturing

process, successive layers are built up on the

silicon wafer. (See generally Becker, Tr. 1116-

32). DRAMs require as many as twenty-two

distinct layers. (Becker, Tr. 1131). Each layer

requires a series of manufacturing steps.

(Becker, Tr. 1131-32). Processing the wafer

takes about four hundred manufacturing steps.

(Becker, Tr. 1118, 1131).

9. The manufacturing process is nonlinear,

meaning that a wafer will reenter different

processing areas of the fab a number of times.

(Becker, Tr. 1118). A processed wafer contains

hundreds of individual DRAM chips. (Becker,

Tr. 1117).

10. The processed wafer is electrically tested

in order to find the good chips. (Becker, Tr.

1132-34). Such testing, however, does not

identify all of the die with disqualifying

defects. More stringent testing is only possible

427a

after the die have been packaged. (Geilhufe,

Tr. 9570).

11. After testing, the wafer is cut into

individual DRAMs. (Becker, Tr. 1132-34). The

individual chips are then bonded to a metal

lattice like structure called a lead frame and

are covered with a black hard plastic mold

compound. (Becker, Tr. 1132-34).

12. After packaging, the good chips are built

into components and tested again. (Becker, Tr.

1135-36).

13. The tested components may also be as-

sembled onto circuit boards to create modules

and are further tested. (Becker, Tr. 1135; see

generally Becker, Tr. 1132-36 (describing the

process of how the chips are built into com-

ponents and connected to modules)).

14. The largest part of a DRAM, approxi-

mately ninety percent of the active area,

consists of the memory array, that is the

memory cells and related circuitry. (Geilhufe,

Tr. 9560). The remaining ten percent consists

of peripheral circuitry. (Geilhufe, Tr. 9560).

Circuitry for implementing the four features at

issue here — programmable column address

strobe (“CAS”) latency, programmable burst

length, dual edge clocking, and on-chip delay

lock loop (“DLL”) — are found in the peripheral

circuitry. (Geilhufe, Tr. 9559).

15. The vast majority of DRAM develop-

ment costs is spent on the memory array

portion of the DRAM, including the manufac-

turing process and equipment development.

(Geilhufe, Tr. 9560-61). Development costs for

428a

the peripheral circuitry are much lower. (Geil-

hufe, Tr. 9560-61).

b. The Various Phases of DRAM

Development

16. The development of the DRAM proceeds

along a number of “phases” and milestones.

Those are the design phase, the layout phase,

the simulation phase, the verification phase,

tape out, initial silicon, the validation phase,

internal qualification phase, and the produc-

tion phase. (Shirley, Tr. 4141-42; Reczek, Tr.

4306-41).

17. In the design phase, the DRAM design-

ers implement the DRAM specification as a set

of circuit designs or schematics. (Shirley, Tr.

4142-43).

18. In the layout phase, the layout designers

take the circuit designs created in the first step

and create a representation of the circuit de-

signs. (Shirley, Tr. 4143).

19. In the simulation phase, the design

engineers simulate the designs in order to

verify that the chips will perform as intended

before they are first manufactured. (Shirley,

Tr. 4144).

20. The verification phase involves ensuring

that the schematics created in the design

phase are in fact represented by the work done

in the layout phase. (Shirley, Tr. 4144-45;

Reczek, Tr. 4309).

21. Tape out involves the process of trans-

ferring the DRAM layout onto masks that will

be used in the fabrication of the DRAM.

429a

(Shirley, Tr. 4145). The collection of individual

masks necessary to fabricate a DRAM design

comprises a mask set. (Shirley, Tr. 4147).

22. A mask contains an image that is

transferred to the wafer through a process of

using light to expose the wafer to the image

pattern in the mask and using gasses to etch

the resulting pattern into the wafer. (Becker,

Tr. 1122-24).

23. At some DRAM manufacturers, includ-

ing Micron Technologies, Inc. (“Micron”), the

physical creation of masks is done by special-

ized firms that provide che service to the

DRAM manufacturers. (Shirley, Tr. 4145-46).

Other DRAM manufacturers, including Infin-

eon Technologies (“Infineon”), produce their

own masks. (Reczek, Tr. 4312).

24. The mask set, once it is received, is used

to create the first physical manifestation of the

DRAM chips on wafers. Those wafers repre-

sent a milestone and are referred to as “initial

silicon.” (Shirley, Tr. 4147).

25. Initial silicon is then tested in the

validation and internal qualification phases to

ensure that the DRAM on the wafers operate

the way they were intended (the validation

phase) and that the DRAM on the wafers

operate appropriately in the expected environ-

ments (the qualification phase). (Shirley, Tr.

4148-49).

430a

c. Design Modification During

DRAM Production

26. The DRAM industry transitions between

different versions of DRAM quite frequently.

As a witness from Micron explained:

Switching from one product to another,

while still using the same core technology,

involves only changing priorities in design

and product engineering and may mean

some differences in our assembly and test

equipment purchases. SDRAM, SLDRAM,

nDRAM all use the same fab equipment

and core DRAM technology. In short, while

the flavors might change, it’s still a DRAM.

(RX 836 at 3) (emphasis added).

B. The Memory Bottleneck Problem

27. Dr. Michael Farmwald, one of the two

founders of Rambus, received his bachelor’s

degree in mathematics from Purdue University

in 1974. (Farmwald, Tr. 8058). He then earned

a Ph.D. in computer science from Stanford

University in 1981. (Farmwald, Tr. 8059).

While a graduate student at Stanford, Dr.

Farmwald was in charge of a supercomputer

project at Lawrence Livermore National Labs.

(Farmwald, Tr. 8059). After obtaining his

Ph.D, he continued to work at Livermore for

four years and then founded a company called

FTL (which stood for “Faster Than Light”),

whose goal was to build very fast computers.

(Farmwald, Tr. 8060-61). In 1988, Dr. Farm-

wald went to the University of Illinois to teach

in the computer science department. (Farm-

wald, Tr. 8063-64).

43la

28. While working as a professor at the

University of Illinois, Dr. Farmwald realized,

and it was a general perception in the DRAM

industry, that developments in microprocessor

technology would lead to significant speed in-

creases in microprocessors while memory chip

performance would not keep up. (Farmwald,

Tr. 8063, 8067). He recognized that the result

of these trends would be a “bottleneck” —

memory technology would limit computer

system performance. (Farmwald, Tr. 8068-69).

29. Moore’s law, named after Gordon Moore,

founder of Intel Corp. (“Intel”), predicts that

processor speeds will increase by a factor of

four every three years. (Farmwald, Tr. 8068).

This “law” has held true for over the last two

decades. (Farmwald, Tr. 8068). The perform-

ance of DRAMs, however, was increasing at a

lesser rate; while DRAMs were fast in com-

parison to microprocessors in the early 1980s,

as an historical matter, DRAM performance

had increased very slowly over time. (Farm-

wald, Tr. 8072).

30. Graphing predicted microprocessor

speeds against memory performance, Dr.

Farmwald predicted an ever increasing gap

between microprocessor performance and

DRAM performance. (Farmwald, Tr. 8071-73).

31. Assuming that the predicted DRAM

speeds were not improved, Dr. Farmwald

projected that the number of DRAMs needed

to support future microprocessors would be-

come extremely large over time. (Farmwald,

Tr. 8073).

432a

32. The increasing number of DRAMs

needed to support faster computers was also

consistent with Dr. Farmwald’s experience

that microprocessors were demanding higher

and higher bandwidth memory systems

(“bandwidth” being the amount of information

that can be transferred over a specific period of

time). (Farmwald, Tr. 8076-79).

33. Dr. Farmwald also plotted the projected

price for computers, which showed that the

cost for computer systems was dropping over

time. (Farmwald, Tr. 8074-75). Comparing

these projected costs with the number of

DRAMs that would be required to support the

bandwidth needs of faster microprocessors, Dr.

Farmwald knew that “there was something

broken” — the costs of the thousands of DRAMs

needed at higher microprocessor speeds would

prevent the decline of computer system prices.

(Farmwald, Tr. 8075-76).

34. Later, a 1992 Rambus “Corporate Back-

grounder” described the issue: “[o]ne of the

most serious problems is the chronic speed

mismatch between processors and main mem-

ory. Designers refer to this as the memory

bottleneck. The data transfer rates of memory

ICs [integrated circuits] lag far behind a proc-

essor’s ability to handle the data.” (RX 81 at 4).

35. To meet the higher bandwidth needs of

microprocessors without the overwhelming

cost of thousands of DRAMs, DRAM perform-

ance had to increase at a higher rate. (Farm-

wald, Tr. 8076).

433a

36. Years later, Dr. Farmwald’s 1988 ob-

servations were recognized by others in the

industry. For example, an April 1992 internal

memorandum of Siemens AG (“Seimens”)

states that “[ajs a result of the trend toward

increasingly faster RISC and CISC processors,

the DRAM interface has become more and

more of a problem for system ‘developers. In

order to eliminate this data transmission rate

bottleneck, various competing concepts regard-

ing the design of newer DRAMs have emerged

....” (RX 285A at 1).

37. Similarly, an Octobe- 1992 article pub-

lished in the Institute of Electrical and

Electronic Engineers, Inc. (“IEEE”) Spectrum

warned, “[i]f the price-to-performance ratio of

computer systems is to keep improving, the

gap in speed between processors and memory

must be closed.” (RX 329 at 1). IEEE Spectrum

is the overall general magazine for the IEEE, a

professional organization of electronic and

electrical engineers. (Prince, Tr. 8972-73). The

article went on to explain that “the accepted

dynamic RAM (DRAM) architectures and

solutions have been pushed to their limits. A

basic change in architecture seems the only

way to obtain an urgently needed increase in

memory speed.” (RX 329 at 1). This article

reflected a general discussion within the in-

dustry in 1992 that computer companies

needed faster DRAMs. (Prince, Tr. 8977-78).

38. Another article in the October 1992

IEEE Spectrum stated, “[i]f dynamic RAMs

and processors are to trade data at close to top

speed, the interface between them must be re-

434a

engineered. .. . None of the types of interfaces

now popular can do this while conserving

power and cost to the desired degree.” (RX 333

at 1).

39. In February 1994, Dr. Betty Prince, a

long-time consultant in the DRAM industry

and the author of five books on DRAM

technologies (Prince, Tr. 8970-72), wrote in an

article published in IEEE Spectrum that “[t]he

mismatched bandwidths of fast processors and

the slower memory chips they must employ are

a problem of long standing. Processors now as

always require more data per unit time than

many standard memory chips have been de-

signed to provide.” (RX 465 at 1). She also

provided a graph showing that this perform-

ance gap was increasing over time. (RX 465

at 1). Dr. Prince agreed that the performance

gap she wrote about created a bottleneck.

(Prince, Tr. 8990-91).

40. Intel saw the memory bottleneck coming

in 1995, and the recognition of this bottleneck

prompted Intel to investigate various memory

technologies in an effort to remedy the situa-

tion. (MacWilliams, Tr. 4929-30).

C. Farmwald’s and Horowitz’s Inventions

Solve the Memory Bottleneck Problem

by Addressing Numerous Issues

41. In 1988, Dr. Farmwald conceived the

general idea of a new memory interface and

protocol (an organization of the bits and timing

of bits transferred by a memory chip) that

would allow a single DRAM chip to have

higher performance than a board Dr. Farm-

435a

wald had designed containing 320 existing

DRAM chips. (Farmwald, Tr. 8086-88).

42. In order to progress beyond his initial

ideas Dr. Farmwald realized that he needed

the assistance of an ex ert in circuit design.

(Farmwald, Tr. 8089). Dr. Farmwald sought

the help of a former colleague — Dr. Mark

Horowitz, a professor at Stanford. (Farmwald,

Tr. 8089-90).

43. Dr. Horowitz had completed both his

bachelors and masters degrees in electrical

engineering from MIT in four years, receiving

the degrees in 1978. (Horowitz, Tr. 8477). After

working for a year at Signetics, he then earned

a Ph.D. in integrated circuit design from

Stanford University in 1983. (Horowitz, Tr.

8477-80). Dr. Horowitz has been a professor

in the electrical engineering and computer

science departments at Stanford University

since the mid-1980’s. (dorowitz, Tr. 8476). Dr.

Horowitz currently holds two endowed chairs

at Stanford. (Horowitz, Tr. 8482).

44. Dr. Farmwald convinced Dr. Horowitz to

take a year’s leave from Stanford to further

explore their ideas. (Farmwald, Tr. 8092-93).

Starting in the spring of 1989, the two worked

from Dr. Horowitz’s Palo Alto home. (Farm-

wald, Tr. 8093-94).

45. Dr. Horowitz’s goal was to build the

fastest possible DRAM interface. (Horowitz,

Tr. 8486). Drs. Horowitz and Farmwald deter-

mined that 500 megahertz (“MHz”) DRAM

operation might be possible, and they worked

toward that goal. (Horowitz, Tr. 8505-06).

436a

46. In creating their inventions, Drs. Farm-

wald and Horowitz had to solve numerous

problems. (Horowitz, Tr. 8487). They realized

that current memory interfaces could not run

at high speeds as a result of electrical issues,

clocking issues, and issues relating to the

protocol, and that they would need innovations

in each of these areas in order to meet their

goal. (Horowitz, Tr. 8487-88).

1. Electrical Issues

47. With respect to electrical issues, Drs.

Farmwald and Horowitz needed to develop

driver and receiver circuitry that could gen-

erate very high-speed signals, and they also

needed to develop a bus that would allow the

signals to propagate. (Farmwald, Tr. 8118-20;

Horowitz, Tr. 8488).

48. Drs. Farmwald and Horowitz developed

a number of solutions to the electrical issues

that arose. First, they realized that reflected

signals from the end of the bus lines would be

a serious problem at high speeds and conceived

the idea of introducing resistors to “terminate”

the bus lines and reduce reflections. (Horowitz,

Tr. 8492-93).

49. Second, Drs. Farmwald and Horowitz

realized that the high voltage signaling then in

use would generate too much power at high

speeds, and they developed low voltage signal-

ing using a particular kind of driver called

a “current mode” or “current source” driver.

(Farmwald, Tr. 8119, 8144-45; Horowitz, Tr.

8494-95; RX 82 at 9).

437a

50. Third, Drs. Farmwald and Horowitz

realized that they could not build a 500 MHz

DRAM with current technology and so, to

transmit data at the highest possible speed,

they conceived the idea of transmitting and

receiving data on both edges of a 250 MHz

clock. (Farmwald, Tr. 8118; Horowitz, Tr.

8495-97).

2. Clocking Issues

51. With respect to clocking issues, Drs.

Farmwald and Horowitz realized from per-

sonal experience that, although current mem-

ory chips were asynchronous, they would have

to develop a synchronous device with mech-

anisms for exercising very tight control over

timing with respect to the clock to make sure

that each bit of data — traveling at a very high

speed — was sampled at the right time. (Horo-

witz, Tr. 8488-89; see infra F. 52-53, 284 for

discussion of asynchronous versus synchronous

devices).

52. Drs. Farmwald and Horowitz decided to

design a synchronous system since the timing

reference provided by a clock could be used to

limit timing uncertainties in the system and

allow for high speed performance. (Horowitz,

Tr. 8499-502).

53. Even in a synchronous system there

remain some timing uncertainties; for exam-

ple, expected delays of the buffers may vary

from DRAM to DRAM due to differences in

their fabrication. (Horowitz, Tr. 8503-04). In

order to have the highest speed possible, Drs.

Farmwald and Horowitz wanted to minimize

438a

this remaining uncertainty to the extent pos-

sible; they therefore came up with the idea of

using a delay locked loop (DLL) or a phase

locked loop (PLL) on-chip. (Farmwald, Tr.

8118; Horowitz, Tr. 8504).

3. The Memory Interface Protocol

54. With respect to the design of the pro-

tocol, additional optimizations developed for

high speed operation included returning a

variable amount of data in response to a

request rather than a single bit of data and by

putting registers and associated control cir-

cuitry directly on the DRAM. (Farmwald, Tr.

8115; Horowitz, Tr. 8489-90).

55. With respect to the protocol, Drs. Farm-

wald and Horowitz again came up with various

innovations. As one example, they decided to

put registers on the DRAM to make the

interface more efficient. (Farmwald, Tr. 8115-

16; Horowitz, Tr. 8506). These registers would

be programmed with parameters, such as the

address range that a particular DRAM would

respond to or the access time of the DRAM.

(Horowitz, Tr. 8507, 8509-10). |

56. Drs. Farmwald and Horowitz wanted to

make the access time variable for two reasons.

First, if the bus were improved so that it could

operate at a faster clock frequency, the access

time of the DRAM could be adjusted so that it

would operate with that faster clock. Second, a

variable access time would allow the access

times of all the DRAMs in a system to be ad-

justed to have the same access time. (Horowitz, _

Tr. 8510-11).

439a

57. As another example of an innovation

related to the protocol, Drs. Farmwald and

Horowitz allowed the response to a request to

include a variable amount of data, a feature

known as “variable block size” or “variable

burst length.” (Farmwald, Tr. 8116-17, 8146;

Horowitz, Tr. 8512; RX 82 at 9).

II. RAMBUS: COMPANY DEVELOPMENT AND

PUBLIC PROMOTION OF TECHNOLOGY

A. The Founding of Rambus

58. Drs. Farmwald and Horowitz founded

“Rambus Inc.” in March of 1990. (CX 545 at 5;

RX 81 at 19). By 1992, its headquarters were

located in Mountain View, California, in Sili-

con Valley. (RX 81 at 1, 3).

59. Rambus is, and at all relevant times has

been, a corporation as “corporation” is defined

by Section 4 of the Federal Trade Commission

Act, 15 U.S.C. § 44; and at all relevant times

has been and is now engaged in commerce as

“commerce” is defined in that same provision.

(Answer, {J 5, 6).

60. Rambus designs, develops, licenses, ar.a

markets both nationally and internationally,

high-speed chip connection technology to en-

hance the performance of computers, consumer

electronics, and communications systems. (An-

swer, J 5). Rambus is a pure-play licensing

company; it does not manufacture DRAM, but

rather uses research and development to in-

vent new DRAM technologies and makes its

money by licensing its technology to others.

(Teece, Tr. 10350-51).

440a

61. For the fiscal year that ended on Sep-

tember 30, 2001, Rambus reported revenues of

approximately $117 million. (Comp., J 5; An-

swer, ¥ 5).

62. Rambus’s founders intended to improve

memory performance through multiple invent-

tions based on modifications of standard

DRAMs (see CX 533 at 2), which could be used

separately or in combination(s). The greatest

performance gains would be realized by using

these inventions in combination. Rambus

DRAM or “RDRAM” is the name for the “revo-

lutionary DRAM architecture and high speed

chip-to-chip data transfer technology” that

incorporates several of Rambus’s inventions,

including its proprietary bus technology. (RX

81 at 3). Each of the various generations of

RDRAM are manufactured in accordance with

specifications established through a collabo-

ration among Rambus and its DRAM partners.

(Farmwald, Tr. 8149, 8241).

63. Early on, Rambus realized that it was

important to its business strategy to protect

the intellectual property rights to its tech-

nology. (CX 535 at 1). Part of its early strategy

to do this was to pursue an application for “a

basic, broad patent filed in all major industrial

nations” and thereafter “follow up with addi-

tional patents on inventions created during the

development of the technology.” (CX 535 at 1).

It was also important to Rambus to enter into

nondisclosure agreements with companies

exposed to its technology. (CX 535 at 1).

64. The only business model that “made any

sense” to Rambus co-founder Michael Farm-

44la

wald “was to patent [the technology], convince

others to build it, and charge them royalties”

because “[w]hen we were first formed, it was

my view that we could not possibly raise

enough money to build DRAMs. DRAM fabs

cost, even back then they cost, [sic] order of

a billion dollars. You couldn’t really build

DRAMs without owning your own fab, and so a

business plan which involved actually building

and selling DRAMs was hopeless, and so from

the very beginning we were a royalty-based

company.” (Farmwald, Tr. 8095; CX 2106 at 27

(Farmwald, Dep.)).

65. Rambus’s primary objective was to com-

mercialize the revolutionary inventions Drs.

Farmwald and Horowitz had created in the

form of an open industry de facto standard,

and to ensure that the standard “didn’t go off

in incompatible directions.” (Farmwald, Tr.

8110, 8125-26, 8148).

66. Rambus contemplated that it would

earn its income by working with DRAM com-

panies to implement the Rambus interface in

their products, and, for that work, get paid

consulting fees (for the time its engineers

spent working with partners) and royalties for

the use of Rambus’s intellectual property that

would be incorporated into DRAM companies’

products. (Farmwald, Tr. 8150).

67. To become and remain a viable com-

pany, it intended to charge low single digit

royalties, which it believed to be fair in light of

the importance of Rambus’s intellectual prop-

erty contribution to the product and the large

442a

size of the DRAM market. (Farmwald, Tr.

8128; CX 1282 at 5).

68. Rambus founder Farmwald knew that

companies never like to pay royalties unless

they have to and they can not “get out of it.”

(CX 2106 at 27 (Farmwald, Dep.)).

1. Securing Venture Capital Funding

69. In an effort to receive funding for the

start-up of Rambus Inc., the founders ap-

proached various venture capital firms: Klei-

ner Perkins, one of the largest venture capital

firms in the world; Merrill Pickard Anderson

and- Eyre; and Mohr Davidow. (Farmwald,

Tr. 8099). As part of the meetings with the

venture capital firms, the founders prepared

presentations and showed them documents,

such as early business plans. (Farmwald, Tr.

8100). These meetings occurred around the

time of a June 1989 RamBus Business Plan.

(Farmwald, Tr. 8100-01; see CX 533).

70. The start-up had significant financial

considerations and according to the June 1989

business plan, “RamBus” founders (Michael

Farmwald, Mark Horowitz), were able to in-

vest $75,000 in “seed money” and were seeking

an additional $1.5 million in equity invest-

ment. (CX 533 at 4). This amount would only

fund the company through “the completion of a

prototype and to the development of [its] initial

DRAM vendor partnerships.” (CX 533 at 4).

Until it signed with its revenue producing

partners, estimated expenses were $100,000

per month. (CX 533 at 5).

443a

71. In March 1990, Rambus Inc. was born

after receiving venture capital funding of $1.86

million from three firms. (CX 545 at 5; RX 81

at 19).

2. Early Business Plan for’ the

Farmwald/ Horowitz Inventions

72. As a 1989 draft business plan explained,

Farmwald and Horowitz hoped to establish a

de facto standard “by offering all interested

DRAM and central processing unit (“CPU”)

vendors a sufficiently low licensing fee (2%)

that it will not be worth their time and effort

to attempt to circumvent or violate the

patents.” (RX 15 at 9).

73. Dr. Farmwald explained, “{wle were

going to try and find customers for our parts,

big customers, and we were going to try and

license all the DRAM makers to build our part

to supply those customers,” which would lead

to de facto standardization. (Farmwald, Tr.

8124-25).

74. The founders intended to use a program

of phased licensing and promotion of its

proprietary RDRAM technology in order to

convince the industry to adopt its proprietary

technology as the industry standard. (Farm-

wald, Tr. 8297).

75. The plan was for their technology to be

an “open standard”; they refused to license its

technology on exclusive terms. (Farmwald,

Tr. 8185; RX 25 at 16).

76. An “open standard” in the DRAM in-

dustry is a standard for which any patents

4444

that apply to it are available on reasonable and

nondiscriminatory terms. (Bechtelsheim, Tr.

5897; CX 2112 at 190-91 (Mooring Dep.)).

77. Farmwald and Horowitz wanted to

avoid what happened to the Sony Betamax,

which was hampered in the market by re-

strictive licensing. (Farmwald, Tr. 8165-66).

Instead, their goal was to license the tech-

nology “openly and fairly to everybody so

everyone is on equal footing with a relatively

low royalty.” (Farmwald, Tr. 8165-66).

78. Their early business plans indicate that

they were aware that it would be necessary

early on to charge lower royalties in order to

foster acceptance of their proprietary tech-

nology. They recognized that there was a

“trade-off of royalty size vs. incentive to de-

velop alternatives” to their technology. (CX 533

at 14).

79. To ensure that the Farmwald/Horowitz

technology was standardized, i.e., that parts

from one manufacturer were interchangeable

with parts from another manufacturer, the

inventors planned to cooperate with their part-

ners (i.e., the licensees who would manufacture

the devices) to ensure that feedback was

propagated to all partners so that everyone

would use the same good ideas instead of cre-

ating customized parts. (Farmwald, Tr. 8148;

see RX 82 at 17).

80. Farmwald and Horowitz believed that

they had compelling, revolutionary ideas, that

their patents would be significant, and that a

small royalty would be palatable given the per-

445a

formance leap of the technology. (Farmwald,

Tr. 8112-13).

81. The key to success for Farmwald and

Horowitz was that they “had to find a number

of high-volume customers and high-volume

producers to produce the part so that it became

the part that everybody was using” in order for

their technology to become a de facto standard.

(Farmwald, Tr. 8140; CX 1750 at 1).

82. To this end, the inventions were de-

signed to be produced using existing DRAM

manufacturing technology. (Farmwald, Tr.

8142-43; RX 82 at 6).

B. The RDRAM Technology

83. Because from the start the founders

believed that “[rJoyalties are the lifeblood of

Rambus” (CX 2106 at 221 (Farmwald, Dep.)),

Rambus placed great importance on promoting

and protecting its proprietary technology. The

Rambus founders “felt we had a very sig-

nificant invention. We felt that the only way to

protect and to extract vaiue from that inven-

tion was to patent it.” (CX 2106 at 28 (Farm-

wald, Dep.)).

84. Rambus saw its proprietary Rambus

DRAM (“RDRAM”) technology as _ offering

dramatic improvements over existing memory

technology of the time. In 1992 it claimed that

RDRAM technology “achieves a ten-fold in-

crease in component throughput” and would

result in “dramatically increasing system

price/performance.” (RX 81 at 3). In addition,

Rambus claimed that use of the RDRAM

technology “assures a smaller system with

446a

fewer components, and provides the user with

a modular, scalable solution.” (RX 81 at 3).

85. The high-speed chip-to-chip data trans-

fer RDRAM technology was intended to be

used not only in memory chips themselves, but

also to be implemented in other chips including

memory controllers, processors, graphics/video

chips and other high performance components

used in virtually every computer system. (RX

81 at 3). The proprietary Rambus technology

was targeted at mainstream applications from

consumer digital video products to desktop

computers and graphics up to massively par-

allel computers. (RX 81 at 3).

86. The RDRAM technology in the early

1990’s included numerous inventions relating

to the bus, the interface between the bus and

computer chips, and the DRAM. The 1992 Cor-

porate Backgrounder makes clear that the

Rambus “solution is comprised of three main

elements: the Rambus Channel, the Rambus

Interface, and the RDRAM.” (RX 81 at 6). The

Rambus Channel refers to the bus, while the

Rambus Interface and RDRAM refer to other

Rambus innovations separate from the bus.

(RX 81 at 7). Each of these elements contain a

number of independent inventions. (RX 81 at

8-11).

87. RDRAM narrow bus technology contem-

plates the use of circuitry on the chips at either

end of the bus connection to optimize the

signals flowing across the connection. (Horo-

witz, Tr. 8488-90). This circuitry contains high-

level logic which implements a protocol for the

447a

chip-to-chip information transfer. (Horowitz,

Tr. 8489-90).

88. One of the ways that RDRAM tech-

nology achieves a high-speed data transfer

over the narrow bus is through “multiplexing,”

which means that the bus can carry different

pieces of information at different points in

time. (Horowitz, Tr. 8620-21). This aspect of

the RDRAM interface protocol means that over

several clock cycies the bus can carry a combi-

nation of address and control and data signals

on one or more of the same bus lines. (Horo-

witz, Tr. 8620-21; see Rhoden, Tr. 402-03).

89. Another aspect of the RDRAM technol-

ogy is the use of a “packetized” data transfer

protocol. (Horowitz, Tr. 8621; Rhoden, Tr.

403-05). This term means that information

is bundled and the bundle may be sent over

multiple clock cycles rather than transmitted

all at once. (Jacob, Tr. 5465; Rhoden, Tr. 403-

04).

90. The RDRAM technology also contains

various other distinctive aspects, including a

clocking system, sometimes referred to as a

loop clock, to assist in controlling the syn-

chronization of the data transfer between chips

(Rhoden, Tr. 404; Horowitz, Tr. 8647), and a

method of physically packaging the RDRAM

memory chips so that multiple chips could be

vertically mounted on one another to occupy a

small space. (Horowitz, Tr. 8623).

91. The RDRAM technology was sufficiently

distinctive that it was widely considered “revo-

lutionary” in the industry and was promoted

448a

as such by Rambus. (Horowitz, Tr. 8571;

Gross, Tr. 2291; Heye, Tr. 5686-87).

C. The 1990 Business Plan

92. Early Rambus investors were informed

that “[t]he primary business of the RamBus

Company” would be to license proprietary

technology “to manufacturers of DRAM chips

and microprocessors”; that “[t]he DRAM mar-

ket is ... highly sensitized to the concept of

standardization”; and that market conditions

were such that there is “the ability to set world

wide standards for the next generation of

DRAM chips and memory systems.” (CX 533

at 9).

93. The purpose of this early draft of its

business plan was to encourage investment by

explaining to investors why Rambus’s technol-

ogy would enable Rambus to be successful in

the existing and future DRAM market. (See

generally CX 533 at 9-10).

94. Investors were told that “the patented

RamBus technology .. . has the opportunity to

establish a single high performance DRAM

standard,” that in part due to “[t}he DRAM

industry’s penchent [sic] for standardization,”

once the Rambus technology was licensed to

“all major vendors,” it would be “extremely

unlikely that any potential competitor would

be able to gain critical mass enough to chal-

lenge” Rambus; and that such considerations,

including the existence of “strong barriers

to entry” restraining “potential competitors,”

made Rambus an “exceptionally attractive

investment opportunity.” (CX 533 at 9).

449a

95. The strength of Rambus’s_ business

model depended also on the strength of its

technological innovations. Indeed, Rambus’s

early filed broad patent application and the

advantage its technology was seen to enjoy by

virtue of being “faster, denser, lower power and

cheaper than any other approach” were touted

to investors as the most significant barriers to

entry for potential, follow-on competitors. (CX

533 at 9). It was the “stiff competition” pre-

sented by Rambus innovative technology as

well as its marketing strategy of licensing all

of the major vendors that it claimed made it

less pervious to competitors than other poten-

tial investment opportunities. (CX 533 at 9):

96. Rambus hired its first (and to date only)

Chief Executive Officer — Geoffrey Tate — who

joined Rambus in May 1990. (CX 545 at 5).

D. RDRAM Promotion and _ Licensing

Strategy

97. By November 1990, Rambus had begun

its efforts to promote and protect its tech-

nology. (CX 535 at 4-5). At that date Rambus

had filed for, but not yet obtained, a base

patent on its technology (CX 535 at 3) and had

entered into license contracts that compelled

partners to use Rambus technology patents

and trade secrets only for use in RDRAM-

compatible chips. (CX 535 at 4-5).

98. By June 1992, Rambus had signed tech-

nology license agreements with NEC Corp.

(“NEC”), Toshiba Corp. (“Toshiba”), and Fu-

jitsu Laboratories, Ltd. (“Fujitsu”). (CX 543A

at 11). By January 1994, Rambus had signed

450a

license agreements with Hitachi, Ltd. (“Hi-

tachi”), Oki Electric Industry Co. (“Oki”),

Lucky Goldstar, and Intel. (CX 547 at 12).

These agreements invoived substantial inter-

action between Rambus and the licensees.

(Farmwald, Tr. 8241).

99. In the course of negotiating with DRAM

manufacturers and others, Rambus encoun-

tered resistence to its business model, and

specifically to royalties. (CX 711 at 13, 61). “A

few systems companies and IC [integrated

circuit] companies have had a very negative

reaction to our business model. Some believe

that it is not ‘fair’ that we are wanting to

charge a royalty on ICs that incorperate our

technology. Others believe our royalty will

make ICS incorporating our technology ‘too

expensive.’ Two specific examples are Sun and

Tseng.” (CX 543A at 14).

100. Rambus limited the use of its license

agreements to so-called RDRAM compatible

uses only. Most companies accepted this term.

Samsung Electronics Co., Ltd. (“Samsung”),

however, insisted on an agreement without

field of use restrictions. (CX 767).

101. In 1994, Samsung recognized that

Rambus’s inventions could be used in non-

compatible Rambus parts, i.e. in parts without

Rambus’s proprietary bus technology. (CX

767). Moreover, Rambus made it clear to

Samsung that Rambus’s intellectual property

rights were not limited to the RDRAM product.

(CX 2078 at 116 (Karp, Dep.)).

45la

E. Presentation of the Rambus Inventions

to the DRAM Industry

1. Rambus Visits to DRAM Manu-

facturers and Systems Companies

102. In 1989-90, Drs. Farmwald and Horo-

witz made visits to many DRAM manufac-

turers and systems companies to try to con-

vince them about the benefits of their approach

and to get feedback from them. (Horowitz, Tr.

8515).

103. Among the DRAM manufacturers that

Drs. Farmwald and Horowitz visited in 1989-

90 were Texas Instruments, IBM, Toshiba,

Fujitsu, Mitsubishi Electric Corp. (“Mitsu-

bishi”), NEC, Matsushita Elect. Indus. Co.,

Ltd. (“Matsushita”), Micron, and Siemens

(whose former semiconductor division is now

Infineon Technologies). (Horowitz, Tr. 8515;

Farmwald, Tr. 8166).

104. Among the systems companies that Drs.

Farmwald and Horowitz visited in 1989-90

were IBM (both a DRAM manufacturer and a

systems company), Sun Microsystems (“Sun”),

Motorola, Apple Computer (“Apple”), SGI, and

Tandem. (Horowitz, Tr. 8515; Farmwald, Tr.

8166-67).

105. The response to the early presentations

in 1989-90 was “just disbelief” that Drs. Farm-

wald and Horowitz would be able to achieve a

500 megabit per second DRAM data rate.

(Horowitz, Tr. 8516). People who listened to

these presentations were also skeptical about

many of the specific features of the technology.

For example, it was felt that putting registers

452a

on a DRAM was too expensive for a commodity

part and that one could not put a phase locked

loop or a delay locked loop on the DRAM itself.

(Horowitz, Tr. 8517).

106. The four inventions at issue in this case

were described in these early presentations.

For example, one of the early presentations

that Dr. Horowitz gave, with slides dated

January 31, 1990, states that the Rambus

interface “allows ‘block mode’ transfer from an

individual DRAM” with “1-1024 byte long

blocks supported.” (RX 29 at 9; Horowitz, Tr.

8518-20). This describes variable block size or

variable burst length. (Horowitz, Tr. 8520).

107. The January 31, 1990 presentation also

describes the use of a delay locked loop on the

DRAM to reduce clock skew. (RX 29 at 33-34;

Horowitz, Tr. 8521-22).

108. The January 31, 1990 presentation also

refers to the dual-edge clock or double data

rate technique. (RX 29 at 34; Horowitz, Tr.

8522-23).

2. Preparation and Description of the

Rambus Inventions Through Various

Technical Publications

109. In the 1990-91 period, Dr. Horowitz

prepared detailed technical descriptions of

the Rambus technology. (Horowitz, Tr. 8523).

These documents were for Rambus’s internal

use and were also used with customers and

potential customers to convince them of the

merits of Rambus technology and to help them

build it. (Horowitz, Tr. 8523-24). These docu-

ments disclose all four of the relevant product

453a

markets in this case: dual-edge clocking, on-

chip DLL, programmable CAS latency, and

programmable burst length.

a. The May 1990 Technical

Description

110. One of these technical descriptions is

dated May 7, 1990 and was generated at about

that time. (RX 63; Farmwald, Tr. 8168-69;

Horowitz, Tr. 8524-25).

111. The May 7, 1990 technical description

described all four of the technological features

at issue in this case. (Horovitz, Tr. 8525-29).

112. For example, the technical description

described dual-edge clocking in a figure with

two input receivers, one clocked by a signal

designated “CLK” (clock) and the other clocked

by the complement of CLK (clock bar), a signal

that is zero when clock is one and vice versa.

(RX 63 at 10; Horowitz, Tr. 8525-26). This

means that one receiver samples an input

when the clock goes high (the rising edge of the

clock) and the other when the clock goes low

(the falling edge). (Horowitz, Tr. 8526).

113. The May 7, 1990 technical description

also described a delay-locked loop on the

DRAM (on-chip DLL feature). (Horowitz, Tr.

8527-28). A figure in the technical description

shows two delay locked loops generating the

internal clocks for Rambus’s design. (RX 63 at

14; Horowitz, Tr. 8527).

114. The May 7, 1990 technical description

also described programmable latency. (Horo-

witz, Tr. 8528). In the “device registers” section

454a

of the document, an “access time” or latency

8528). “Latency” refers to the time between

request and response. (Horowitz, Tr. 8530).

The document explains that a fixed value for

latency “does not allow for technology improve-

ments,” and, consequently, the Rambus system

“set[s] the time between request and response

during system reset.” (RX 63 at 5-6; Horowitz,

Tr. 8530-31). In other words, the value in the

access time or latency register would be fixed

when the system was started up and probably

would not be changed after that time. (Horo-

witz, Tr. 8531).

115. The May 7, 1990 technical description

also described variable burst length. (Horo-

witz, Tr. 8528-29). The document contains a

table showing a variable number of bytes in

the block size or burst length depending on the

value in the “BlockType” field. (RX 63 at 21;

Horowitz, Tr. 8528-29).

b. The November 1990 Technical

Description

116. A later Rambus technical description,

dated November 5, 1990, was’ generated

around that time. (RX 94; Farmwald, Tr. 8169;

Horowitz, Tr. 8535).

117. The November 5, 1990 technical de-

scription was sent to Siemens (now Infineon).

(RX 99; Farmwald, Tr. 8169-70).

118. The November 5, 1990 technical de-

scription described dual-edged clocking. First,

the document contains the same figure relating

to inputting data on both edges of the clock as

455a

in the May 7, 1990 description. (RX 63 at 10;

RX 94 at 15; Horowitz, Tr. at 8535-36). Second,

the document shows that the output data is

also being transmitted on both edges of the

clock. (RX 94 at 19; Horowitz, Tr. 8536).

119. The November 5, 1990 technical de-

scription described two alternatives for the

DRAM clock circuitry. One alternative was to

use a phase locked loop. (RX 94 at 45; Horo-

witz, Tr. 8536-37). The other alternative was to

use delay locked loops. (RX 94 at 46; Horowitz,

Tr. 8537).

120. The November 5, 1990 technical de-

scription described variable latency using a

data delay field in the request packet. (RX 94

at 59; Horowitz, Tr. 8537-38).

121. The November 5, 1990 technical de-

scription described variable block size or burst

length with a table similar to that in the May

7, 1990 technical description. (RX 63 at 21; RX

94 at 60; Horowitz, Tr. at 8538).

c. Siemens Responds With a List of

Questions About Rambus Tech-

nology

122. Both Dr. Farmwald and Dr. Horowitz

received feedback from Siemens regarding the

November 5, 1990 technical description. (RX

102; RX 117; Farmwald, Tr. 8171-72; Horowitz,

Tr. 8541-42).

123. A fax from K. Horninger of Siemens to

Dr. Farmwald, dated December 7, 1990, con-

tained a detailed list of questions relating to

456a

the November 5, 1990 technical description.

(RX 102; Farmwald, Tr. 8171-73).

124. A fax from H.J. Neubauer of Siemens to

Dr. Horowitz, dated January 29, 1991, stated

“Dear Dr. Horowitz, concerning the RAMBUS

Technical Description some basic items re-

mained open. In the following we present a list

of detailed questions to you which we would

like to get answered.” (RX 117 at 2; Horowitz,

Tr. 8542).

125. A number of the questions in the fax

that Siemens sent to Dr. Horowitz related to

the four features of Rambus technology at

issue in this case. (See RX 117).

126. Question number one in the Siemens

fax asked about the details of how eight bits of

data would be transmitted by the DRAM and

relates to Rambus’s variable block size feature.

(RX 117 at 2; Horowitz, Tr. 8543-44).

127. Question number two in the Siemens

fax asked about the implementation of variable

latency in the Rambus technology. (RX 117 at

2; Horowitz, Tr. 8544).

128. Another question in the Siemens fax

referenced Figure 13 on internal page 14 of the

November 5, 1990 technical description. (RX

117 at 4). That figure showed dual-edge clock-

ing or double data rate on the output. Dr.

Horowitz’s understanding was that Siemens’s

question related to the implementation of

the double data rate drivers as shown in the

November 5, 1990 technical description. (RX

94 at 19; RX 117 at 4; Horowitz, Tr. 8546).

457a

129. Another question in the Siemens fax

referenced Figure 28 on internal page 41 of the

November 5, 1990 technical description. (RX

117 at 4). That figure shows a delay locked

loop and Siemens’s question was about the

delay locked loop. (RX 94 at 46; RX 117 at 4;

Horowitz, Tr. 8546).

d. The April 1991 #£Technical

Description

130. A still later Rambus technical de-

scription was released on April 1, 1991 and

was a more complete version with many more

technical details. (RX 130; Farmwald, Tr. 8171;

Horowitz, Tr. 8538).

131. The April 1, 1991 technical description

described dual-edged clocking. (RX 130 at 36;

Horowitz, Tr. at 8539).

132. The April 1, 1991 technical description

described using a phase locked loop on the

DRAM. (RX 130 at 56; Horowitz, Tr. 8539).

133. The April 1, 1991 technical description

described programmable latency through the

use of a “read delay” or latency register. (RX

130 at 94; Horowitz, Tr. 8539-40).

134. The April 1, 1991 technical description

described variable block size or burst length,

with the value in a “count” field representing

the number of bytes to be transferred. (RX 130

at 64; Horowitz, Tr. at 8539).

F. The March 1992 Press Events

135. On March 9, 1992, Rambus held simul-

taneous events in the Silicon Valley and in

Tokyo to publicly announce its technology and

458a

its business plan. (Farmwald, Tr. 8182-84;

RX 67 at 1). Prior to this date, Rambus had

presented its technology to companies on an

individual basis and had secured licenses from

three of the top five DRAM manufacturers:

Fujitsu, NEC, and Toshiba. (RX 67 at 2).

136. The press release announcing these

events stated that Rambus’s_ revolutionary

technology would offer a tenfold improvement

over traditional DRAMs and would solve the

memory bottleneck. (RX 67 at 1). The press

release also described Rambus’s business plan

as licensing its technology in return for license

fees and royalties. (RX 67 at 2). By controlling

the Rambus interface standard, Rambus would

ensure compatibility. (RX 67 at 2). The press

release also made it clear that Rambus’s “open

standard” would be “available for license by

any IC [Integrated Circuit] company.” (RX 67

at 2; see also Farmwald, Tr. 8185).

137. At the events, Rambus made available a

“Corporate Backgrounder” that provided an

overview of Rambus’s business strategy and its

technology. (RX 81; Farmwald, Tr. 8186). The

Backgrounder explicitiy detailed Rambus’s in-

tellectual property strategy: “Rambus Inc. is

fully protecting the intellectual property rights

of its technolegy by filing basic, broad patents

in all major industrial nations around the

world.” (RX 81 at 3).

138. Later in this same public document,

there are descriptions of Rambus’s technology.

(RX 81 at 8-11). The Backgrounder states

that Rambus’s “dramatic performance im-

provements were achieved through numerous

459a

technical breakthroughs” and then proceeds to

describe “[s]ome of the major technical high-

lights of the Rambus solution.” (RX 81 at 8).

The technology descriptions included the use of

dual-edge clocking: “[a]n innovative electrical

interface permits the Rambus Channel to oper-

ate at 500 Megabytes/second by using both

edges of a 250 MHz clock.” (RX 81 at 8).

Moreover, the technology descriptions explic-

itly state that Rambus used the on-chip

PLL/DLL technology: “[c]lock skew and capa-

citive loading are minimized by a phase lock

loop circuit on board both the master and the

RDRAM.” (RX 81 at 8).

139. The Backgrounder also made it clear

that Rambus’s technology was divided into

three distinct elements of the memory system:

the Rambus Channel (the high-speed bus); the

Rambus Interface (the circuitry that connects a

device, such as a controller or DRAM, to the

bus); and the Rambus DRAM (the memory

itself). (RX 81 at 7; Farmwald, Tr. 8188-90).

140. The Backgrounder also stated that

Rambus’s business strategy was to license its

technology, work with the licensee to help

implement the technology, and to receive fees

and royalties in return. (RX 81 at 3; see also

Farmwald, Tr. 8186-87).

141. Later that year, at the invitation of

Betty Prince, a long-time consultant in the

DRAM industry (Prince, Tr. 8970-72, 8986-87),

Dr. Farmwald and David Mooring of Rambus

published an article in the October 1992 issue

of IEEE Spectrum, which gave a brief de-

scription of the Rambus technology and stated

460a

that the “technology behind the architecture

can be licensed for a royalty fee comparable to

that for other patented technologies.” (RX 332

at 1).

142. During the early 1990’s Rambus’s busi-

ness model was well known in the industry.

Brett Williams, a JEDEC Solid State Tech-

nology Association (“JEDEC”) representative

for Micron testified that in 1992, “I knew it

was [Rambus’s] business model to patent their

technology, and that’s how they would gain

their revenues.” (Williams, Tr. 857). Similarly,

Martin Peis] of Infineon stated that he was

aware of Rambus’s business model in the early

1990’s and expected Rambus to get patents to

cover its technology. (Peisl, Tr. 4505).

143. According to Andreas Bechtelsheim,

formerly of Sun Microsystems, Rambus made

very clear to Sun that it intended to seek

patent coverage for all of its inventions and

developments, and Rambus explained to vari-

ous companies, including Sun, that it was seek

ing patent coverage for its inventions because

it intended to obtain revenue or earn revenue

through licensing its technology to both mem-

ory manufacturers and system manufacturers.

(Bechtelsheim, Tr. 5819).

G. Press Coverage: The March 1992

Microprocessor Report Article

144. In connection with the public announce-

ment of Rambus’s technology and its business

plan in March 1992, Rambus provided infor-

mation to the press regarding Rambus’s inven-

46la

tions, and numerous articles about Rambus

appeared. (RX 1446).

145. Many of these articles provided a sig-

nificant amount of technical detail. For exam-

ple, an article entitled “Rambus Unveils Revo-

lutionary Memory Interface” in the March 4,

1992 Microprocessor Report describes Ram-

bus’s technology in some depth and described

three of the four features of Rambus technol-

ogy at issue here, as well as aspects of the

fourth. (RX 1446 at 22-26).

146. The article states that the “Rambus

Channel is a 500-Mbyte/s interface, operating

with a 250-MHz clock and transferring a byte

of data on each clock edge” and that a “phase-

locked loop on each Rambus device limits clock

skew within the chip.” (RX 1446 at 22, 23).

147. The article also states that the “six-byte

request packet encodes a 36-bit address, a 4-bit

operation code, and 8-bit transfer length count

(in bytes). Byte addressing and block sizes of

up to 256 bytes are supported.” (RX 1446

at 24).

148. The article also notes that “control

registers” on the DRAM can be used to specify

certain parameters. (RX 1446 at 23).

H. Rambus’s Disclosure of Inventions

Through Public Documents

1. The 1992 Marketing Brochure

149. In early 1992, Rambus produced and

distributed its first marketing brochure about

Rambus technology. (RX 2183; Horowitz, Tr.

8547). The 1992 marketing brochure describes

462a

the four features of Rambus technology at

issue here. (Horowitz, Tr. 8547-48).

150. The 1992 marketing brochure states

that the “heart of [the Rambus] Interface is

high performance PLL (phase-locked-loop) cir-

cuitry which provides the clocks for trans-

mitting and receiving Rambus Channel data.”

(RX 2183 at 6).

151. The 1992 marketing brochure describes

variable burst length, because data transfers

could involve a variable amount of data, indi-

cating: “[t]ransfers of 1 to 256 Bytes per Re-

quest.” (RX 2183 at 7).

152. The 1992 marketing brochure describes

dual-edge clocking, stating that “[dJata effec-

tively transferred on both edges of the clock.”

(RX 2183 at 9).

153. The 1992 marketing brochure describes

programmable latency, stating that “the Read

Data Packet is returned a time ReadDelay

after the Request Packet” and that this delay

value is “programmed into the configuration

registers of all devices during system initial-

ization.” (RX 2183 at 11).

2. Publications Describing the First

Rambus DRAM

154. The first Rambus DRAM was a 4.5

megabit Rambus DRAM produced by Toshiba

in the 1991-92 time frame. (Horowitz, Tr.

8548-49).

155. A paper about the Toshiba 4.5 megabit

Rambus DRAM was presented at the 1992

International Symposium on VLSI Circuits

463a

(VLSI Circuits Symposium) and published in

the proceedings of that symposium. (RX 301 at

76-77; Horowitz, Tr. 8552-54).

156. The VLSI Circuits Symposium is held

annually and is one of the top two conferences

in the world for circuit designers. (Horowitz,

Tr. 8552). The “technical program committees”

of the Symposium read all the papers sub-

mitted and choose the better ones for pub-

lication at the conference. (Horowitz, Tr. 8552-

53). The technical program committees for the

1992 VLSI Circuits Symposium that selected

the paper about the Toshiba 4.5 megabit Ram-

bus DRAM included representatives from IBM;

Texas Instruments; Siemens AG; Sun Micro-

systems; Intel; Hitachi; Samsung; Matsushita;

Mitsubishi; Fujitsu Laboratories, Ltd.; Sanyo

Electric Co., Ltd.; Oki; and NEC. (RX 301 at 5).

157. The paper published in the proceedings

of the 1992 VLSI Circuits Symposium about

the Toshiba 4.5 megabit Rambus DRAM dis-

cusses the four features of Rambus technology

at issue in this case. (Horowitz, Tr. 8554).

Figure 2 of the paper shows a block size trans-

fer and read latency. (RX 301 at 77; Horowitz,

Tr. 8555). Figure 3 of the paper shows double

data rate input receivers. (RX 301 at 77;

Horowitz, Tr. 8555). The paper also states that

“(tlo eliminate skew caused by the internal cir-

cuitry, the DRAM contains two PLLs.” (RX 301

at 76; Horowitz, Tr. 8555).

158. At the end of the 1992 VLSI Circuits

Symposium, the authors of the top papers were

invited to provide a longer version to be pub-

lished in the Journal of Solid State Circuits.

464a

(Horowitz, Tr. 8555-56). The Journal of Solid

State Circuits is the most widely read journal

for circuit-designers. (Horowitz, Tr. 8555-56).

The paper about the Toshiba 4.5 megabit Ram-

bus DRAM was selected, and a longer version

of that paper was published in the Journal of

Solid State Circuits in April 1993. (RX 385;

Horowitz, Tr. 8556).

I. Presentations of the Proprietary

RDRAM Technology and Nondisclo-

sure Agreements

159. Continuing for many years, Rambus

pursued a strategy of actively promoting its

proprietary RDRAM technology to companies

that were in a position to manufacture memory

chips or related chipsets. Rambus also pro-

moted RDRAM to others, including systems

companies. (See Crisp, Tr. 2931; CX 543A at 1,

3, 7-8).

160. Rambus’s efforts to promote adoption of

its proprietary RDRAM technology included

making presentations concerning the proprie-

tary RDRAM technology to memory chip man-

ufacturers and other firms. (E.g. CX 2107 at 63

(Oh, Dep.); Bechtelsheim, Tr. 5818-19; Kellogg,

Tr. 5052-53).

161. In connection with such efforts, Rambus

commonly entered into nondisclosure agree-

ments that prohibited the firms from disclosing

information concerning the proprietary Ram-

bus technology to others without the consent of

Rambus. (Bechtelsheim, Tr. 5818-19; Rhoden,

Tr. 521; Kellogg, Tr. 5052-53). Rambus’s pres-

entations often included a discussion of the

465a

patent protection Rambus was seeking for its

inventions. (CX 2079 at 83 (Mooring, Dep.); CX

2111 at 314-15, 316-18, 319-20, 320-21, 322-24

(Tate, Dep.)).

162. In April 1992, Gordon Kelley of IBM

attended a presentation by Rambus at IBM

comparing the proprietary Rambus RDRAM

technology with Synchronous Dynamic Ran-

dom Access Memory (“SDRAM”). (G. Kelley,

Tr. 2535).

163. Desi Rhoden was employed at Hewlett-

Packard (“HP”) when he began to learn about

the Rambus technology in the early 90’s.

(Rhoden, Tr. 396). Rambus came to HP to give

a presentation about its new memory that it

was developing. (Rhoden, Tr: 396). The presen-

tation was made pursuant to a nondisclosure

agreement between Rambus and HP. (Rhoden,

Tr. 521). Although Rambus did not say any-

thing at that presentation about pending

Rambus patent applications, Rhoden assumed

that Rambus probably did have patent appli-

cations. (Rhoden, Tr. 521).

164. Andreas Bechtelsheim, a Vice-President

for technology at Sun (Bechtelsheim, Tr. 5752),

was involved in presentations and discussions

with Rambus and understood that Rambus

had patent rights that covered its proprietary

RDRAM technology. (Bechtelsheim, Tr. 5828-

29; 5841-42). Rambus “made clear [to Bechtel-

sheim] that they were going to protect any

patent on their memory technology because

that was their business model.” (Bechtelsheim,

Tr. 5829).

466a

165. Mark Kellogg, an employee of IBM,

learned about Rambus technology through a

presentation by Rambus to IBM in the early

1990’s. (Kellogg, Tr. 5017, 5052-53).

166. Terry Lee, an employee at Micron,

learned about Rambus technology in part from

a meeting with Rambus held in 1995. (Lee, Tr.

6601-02). Following the meeting, he and a

colleague, Kevin Ryan, reviewed selected pa-

tent abstracts. (Lee, Tr. at 6607-08). Lee con-

cluded that the patents appeared to apply

specifically to the RDRAM bus structure. (Lee,

Tr. at 6610-11). In March of 1997, Lee ex-

pressed concerns to the JEDEC JC 42.3 com-

mittee that a double data rate SDRAM (“DDR

SDRAM”) presentation “looked like” one of the

Rambus patents he had reviewed in 1995.

(Lee, Tr. 6956-59).

J. The June 1992 Business Plan

167. By June 1992, Rambus CEO Geoffrey

Tate transmitted to the Rambus Board of

Directors a comprehensive five-year business

plan, which, he explained, was based on “in-

puts from ail of the executives.” (CX 543A

at 1). As reflected in the “Executive Summary”

of this June 1992 Business Plan, Rambus’s

strategy was to:

develop a breakthrough technology with

high value added in a large percentage of

computer, communications, and consumer

digital systems products;

establish strong intellectual property bar-

riers; ...

467a

to license the technology for integration

onto high volume ICs of all major IC com-

panies and to have license fees cover the

costs of technology and market develop-

ment;

to establish Rambus as the new interface

standard for systems requiring high per-

formance at low cost; .. .

to establish a very high profit stream of

technology royalties; [and]

to continually improve on Rambus Tech-

nology through minor and major enhance-

ments....

(CX 543A at 3).

K. Rambus Patent Applications

1. The ‘898 Patent Application

168. Rambus filed patent application serial

no. 07/510,898 (the ‘898 application) in the

United States Patent and Trademark Office

(“PTO”) on April 18, 1990. (CX 1451 at 1-2;

Nusbaum, Tr. 1507). The ‘898 patent appli-

cation included a descriptive portion, called the

“specification,” that was sixty-two pages long,

and included fifteen original drawings. (CX

1451 at 3-63, 140-50). The ‘898 patent appli-

cation contained one-hundred fifty claims. (CX

1451 at 64-125).

169. In connection with the prosecution of

its ‘898 patent application, Rambus was issued

a communication by the patent examiner at

the PTO containing a restriction requirement.

(Nusbaum, Tr. 1511).

468a

170. A restriction requirement reflects that

the examiner has reviewed the application and

determined that the application contains

claims describing multiple “independent and

distinct inventions.” The applicant is required

to elect which of the claimed inventions it

wishes to pursue in the application. (Nusbaum,

Tr. 1510).

171. The restriction requirement received by

Rambus was an eleven-way restriction require-

ment; Rambus responded by restricting its

original application and filing ten divisional

patent applications on March 5, 1992, all of

which claimed priority based on the filing date

of the original ‘898 application, April 18, 1990

(Nusbaum, Tr. 1511-12; First Set of Stipula-

tions, Stip. 22).

172. Over time, Rambus filed numerous

additional continuation and divisional patent

applications claiming priority based on the

filing date of the original ‘898 application. (See

First Set of Stipulations, Stip. 22).

173. Prior to June 1996, Rambus filed a total

of seventeen continuation and divisional pa-

tent applications claiming priority based on

the filing date of the original ‘898 application,

and had been issued six United States patents

on such applications. (First Set of Stipulations,

Stip. 22).

174. As of April 2003, Rambus had filed

sixty-three continuation and divisional patent

applications claiming priority based on the

filing date of the original ‘898 application, of

469a

which ten were still pending. (First Set of

Stipulations, Stip. 22).

175. As of April 2003, at least 43 United

States patents had been issued to Rambus

from continuation and divisional applications

claiming priority to the original ‘898 appli-

cation. (First Set of Stipulations, Stip. 13).

176. Over time, various of the Rambus

continuation and divisional patent applications

claiming priority to the ‘898 application em-

bodied changes and amendments to the claims

made in the original ‘898 application and came

to describe aspects of the original invention.

(See, e.g., Crisp, Tr. 2927-28).

177. The patents that Rambus has asserted

against DRAM manufacturers have all issued

from applications that are continuations or

divisionals stemming from the original ‘898

application and all share a specification with

that original application. (First Set of Stipu-

lations, Stip. 22; Nusbaum, Tr. 1513-14).

178. Pursuant to the “written description”

requirement for a patent’s validity, the PTO

determined that the claims of these patents

were supported by the specification of the orig-

inal ‘898 application. (Nusbaum, Tr. 1611-14).

2. The ‘703 Patent

179. Rambus’s first United States patent,

U.S. Patent No. 5,243,703 (“the ‘703 patent”),

issued on September 7, 1993. (RX 425). Ram-

bus disclosed the ‘703 patent to JEDEC during

a committee meeting in September 1993. (First

Set of Stipulations, Stip. 11). The ‘703 patent

470a

was subsequently added to the “patent track-

ing list” maintained by JEDEC, where it was

described as involving a “Sync Clock.” (JX 18

at 18).

180. The “703 patent can be traced back to a

divisional application of the original ‘898 ap-

plication. (RX 425 at 1; Fliesler, Tr. 8812).

181. The written description and drawings of

the ‘703 patent, like all the issued patents that

claim priority to the ‘898 application, are sub-

stantially the same as the written description

and drawings in the ‘898 application. (RX 425

at 1; CX 1451 at 1; Fliesler, Tr. 8812, 8817).

Thus, the “703 patent contains the same de-

scriptions of technologies as in the ‘898 appli-

cation and PCT application. (RX 425 at 7, 8, 9,

14-17, 21; Fliesler, Tr. 8819-20).

182. In addition to listing the original ‘898

application, the “703 patent’s written descrip-

tion also contains a list of the nine other

divisional applications stemming from the ‘898

application that were pending at the time. (RX

425 at 11; Fliesler, Tr. 8813-14).

3. The PCT Application

183. On April 16, 1991, Rambus filed an

international patent application pursuant to

the Patent Cooperation Treaty (the “PCT

application”). (CX 1454 at 1).

184. The PCT application is identical in all

material respects to the ‘898 application. In

particular, the PCT application contains the

same written description, drawings, and

47la

claims as the ‘898 application. (CX 1451; CX

1454; Fliesler, Tr. 8811).

185. The PCT application was published and

made publicly available as of October 31, 1991.

(CX 1454 at 1; First Set of Stipulations, Stip.

8). Several JEDEC members obtained the PCT

application in the early 1990’s, including Mit-

subishi and IBM. (RX 379A at 1; RX 201 at 1).

4. The ‘898 and PCT Applications

Describe Numerous Inventions

186. The ‘898 and PCT applications each

contain a lengthy disclosure consisting of a

sixty-two page written description, fifteen

drawings, and one hundred and fifty claims.

(CX 1451, CX 1454).

187. The written description of the ‘898 and

PCT applications contain numerous headings

and subheadings, such as “Device Address

Mapping,” “Bus,” “Protocol and Bus Opera-

tion,” “Retry Format,” “Bus Arbitration,” “Sys-

tem Configuration/Reset,” “ECC,” “Low Power

3-D Packaging,” “Bus Electrical Description,”

“Clocking,” “Device Interface,” “Electrical In-

terface - Input/Output Circuitry,” and “DRAM

Column Access Modification.” (CX 1451 at 18,

20, 21, 30, 32, 37, 40, 43, 45, 47, 54; CX 1454 at

18, 20, 21, 30, 32, 37, 41, 44, 46, 48, 55).

188. Although the applications describe how

an entire system is to be put together, they

also describe numerous technical features that

can be used independently of one another and

of the system. (Fliesler, Tr. 8788-89).

472a

189. The ‘898 and PCT applications note

that, although a preferred implementation of

the invention contains 8 bus data lines, “[p]er-

sons skilled in the art will recognize that 16

bus data lines or other numbers of bus data

lines can be used to implement the teaching

of this invention.” (CX 1451 at 10; CX 1454

at 10).

190. A person of ordinary skill in the art to

which the ‘898 and PCT applications pertain

would have an electrical engineering degree

and at least two to three years of experience in

designing computer memory circuits. (Fliesler,

Tr. 8779-80; Nusbaum, Tr. 1613).

191. It was Dr. Horowitz’s understanding

when the patent application was filed that the

various solutions to problems described in the

application could be used independently of one

another. Thus, if one did not want quite the

level of performance that Drs. Farmwald and

Horowitz envisioned, one could use only a sub-

set of the techniques described in the patent

application. (Horowitz, Tr. 8514-15).

192. Dr. Farmwald never thought of his

ideas as implementing a “narrow” bus. (Farm-

wald, Tr. 8143). Rambus originally used a 9-bit

wide bus because that corresponded to the

number of pins that could fit on the edges of

the chips that existed at the time; later

Rambus used wider buses because more pins

could be placed on the chip. (Farmwald, Tr.

8143-44). While some of the inventions of

Drs. Farmwald and Horowitz might enabie

narrower busses to work better, the inventions

473a

are not specific to a particular bus width.

(Farmwald, Tr. 8144).

193. A March 12, 1993 Mitsubishi memo-

randum begins by stating that a “need has

arisen to evaluate in detail all of the claims in

a patent being applied for by Rambus (1

patent, a total number of claims is 150).” (RX

2214A at 1). The memorandum goes on to list

guidelines for this evaluation, including “1) Do

not discuss Rambus interface. 2) Determine

whether or not any other areas contain tech-

nologies that will be important in increasing

memory speed in the future ” (RX 2214A at 1).

194. A June 10, 1993 Mitsubishi document

with the heading “RAMBUS Patent (summary

of responses)” states: “[i]n addition to the tech-

nologies of narrower bus width and communi-

cation by protocol that are described above, the

RAMBUS patent includes a variety of require-

ments such as memory system configuration,

packaging method, and device configuration,

and it can be achieved through a combination

of these factors.” (RX 406 at 4). The document

continues: “[t]he individual technologies that

appear in the RAMBUS patent will be used

independently in the future.” (RX 406 at 4).

a. Description of Access Time

Registers

195. The ‘898 application and the PCT

application describe access time registers that

store latency, that is tre amount of time be-

tween receiving a request and driving data

onto the bus in response to that request. (CX

1451 at 16, 23; CX 1454 at 16, 23; Jacob, Tr.

5481). The applications state that “|eJach slave

474a

may have one or several access-time registers,”

where “slave” can refer to a DRAM. (CX 1451

at 16; CX 1454 at 16; Jacob, Tr. 5649).

196. In common use, programmable CAS

latency in the mode register of an SDRAM is

set at initialization. (Jacob, Tr. 5648-49). The

‘898 application and PCT application state

with respect to the access time registers (and

other registers): “[m]Jost of these registers can

be modified and preferably are set as part of an

initialization sequence.” (CX 1451 at 16; CX

1454 at 16).

197. A Mitsubishi document headed “Assess-

ment of Rambus Patents (Second Half)” states

next to the numbers 95, 97 and 103: “Mod-

ifiable Access Time Register (Similar to

SDRAM latency control).” (RX 2213A at 25,

27). Claim 103 of the PCT application (and ‘898

application) refers to a “modifiable access-time

198. In a claim-by-claim analysis of the PCT

application produced by Mitsubishi, a marginal

note identifies claim 103 of the application as

relating to latency and SDRAM. (RX 2213A at

7, 9). The analysis further indicates that

Mitsubishi determined that this claim relating

to latency in SDRAMs was particularly im-

portant, for Claim 103 was marked “A.” (RX

2213A at 7, 9). A later page of the document

explains that an “A” grade means that a

technology is “important for increasing DRAM

speed.” (RX 2213A at 27).

475a

b. Description of Block Size

199. The ‘898 application and the PCT

application describe varying the “block size,”

that is the amount of data transmitted in

response or received in response to a request.

(CX 1451 at 29-30; CX 1454 at 29-30; Jacob,

Tr. 5477-78). The applications each state that

“BlockSize [0:3] specifies the size of the data

block transfer.” (CX 1451 at 29; CX 1454

at 29). The applications each contain a table

showing the “Number of Bytes in Block”

corresponding to the value in the “BlockSize”

field. (CX 1451 at 30; CX 1454 at 30).

200. “Burst length,” as the term is used in

SDRAMs, refers to the amount of data to be

transferred per read or write transaction.

(Rhoden, Tr. 379-80; Jacob, Tr. 5396-97.)

Likewise, “block size,” encodes the amount of

data to be transferred per read or write

transaction. (Jacob, Tr. 5477). The two terms

describe the same function and are used inter-

changably. (Horowitz, Tr. 8661-62; Geilhufe,

Tr. 9643).

c. Description of Bus Clock

201. The ‘898 and PCT applications state:

“[cllock distribution problems can be further

reduced by using a bus clock and device clock

rate equal to the bus cycle data rate divided by

two, that is, the bus clock period is twice the

bus cycle period. Thus, a 500 MHz bus pre-

ferably uses a 250 MHz clock rate.” (CX 1451

at 49: CX 1454 at 50). If clock rate is half the

data rate on the bus, both edges of the clock

476a

must be used to transmit data. (Fliesler, Tr.

8801-02).

202. Figure 10 in the ‘898 and PCT appli-

cations shows two input receivers clocked by

“clock” and “clock bar” as in the Rambus tech-

nical descriptions. (CX 1451 at 147; CX 1454 at

148; Fliesler, Tr. 8799). If “clock bar” is high

when “clock” is low, and vice versa, data is

input on both the rising and falling edges of

clock. (Fliesler, Tr. 8799-800).

203. Figure 13 in the ‘898 and PCT ap-

plications shows a timing diagram with data

being input, as indicated by the arrows along

the bottom of the figure, on both the rising and

falling edges of the clock. (CX 1451 at 149; CX

1454 at 150). Howard Sussman, the JEDEC

representative for Sanyo and formerly the

JEDEC representative of NEC, testified that

Figure 13 of the PCT application shows to him

that “input being sampled on the high and low

edge of the clock” and that is “double data rate

input.” (Sussman, Tr. 1322, 1467-68).

d. Description of Variable Delay

Circuitry With a Feedback Loop

204. Figure 12 of the ‘898 and PCT ap-

plications describes variable delay circuitry

and a feedback loop. (CX 1451 at 148; CX 1454

at 149; Jacob, Tr. 5649-50).

205. When Joel Karp, then of Samsung,

reviewed Rambus’s PCT application in 1991,

Figure 12 “jumped out” at him as evidencing a

DLL. (CX 2078 at 119 (Karp Micron Dep.); CX

2114 at 276-77 (Karp Dep.)).

477a

206. In its license negotiations with Rambus

in 1994, Joel Karp felt that Samsung was

motivated to seek a non-assertion provision for

non-Rambus-compatible uses of Rambus’s in-

ventions because of the on-chip DLL shown in

Rambus’s PCT application. (CX 2078 at 107-

08, 119-20 (Karp, Micron Dep.)).

5. Review of the ‘898 or PCT

Application Should Have Raised

Concerns That Rambus Might Be

Able to Obtain Claims Over the Four

Technologies at Issue

207. A person of ordinary skill in the art or a

patent lawyer reviewing the ‘898 application

or PCT application would have realized that

Rambus might have claims broad enough to

cover programmable CAS latency, program-

able burst length, dual-edge clocking, and on-

chip DLL. (Fliesler, Tr. 8784-85, 8810-11).

208. An experienced DRAM designer review-

ing the PCT application would reach the

conclusion that there is considerable similarity

in form and function between programmable

latency, variable burst length, dual-edge clock-

ing, and on-chip DLL as described in the PCT

application and the corresponding features in

SDRAMs or DDR SDRAMs. (Geilhufe, Tr.

9556-57).

209. If an experienced DRAM designer work-

ing on designing an SDRAM incorporating pro-

grammable latency and burst length in the

early 1990’s had reviewed the PCT application,

he likely would have become concerned that

Rambus might have claims to those features

478a

and would have raised the issue with man-

agement. (Geilhufe, Tr. 9558).

210. A manager faced with this issue, in

light of the potential for substantial economic

consequences if a DRAM design infringes a

patent, would likely have gathered additional

technical analysis from specialists and, if there

remained a concern, would have taken the

issue to corporate counsel for a careful review.

(Geilhufe, Tr. 9558-59).

211. When Mitsubishi reviewed the PCT

application, it undertook an in-depth study. A

March 3, 1993 Mitsubishi memorandum re-

quests cooperation on evaluating Rambus’s

PCT patent application because they “realized

that the technology is related not only to

stand-alone semiconductor devices but also to

systems.” (RX 379A at 1).

212. A June 10, 1993 Mitsubishi document

stressed the need for expert analysis of Ram-

bus’s patent application to determine the scope

of the claims, particularly as to individual

technologies’ disclosed in the patent

application: “[t]here is a need to examine the

specifications of the patent claims to determine

whether individual technologies used

independently will infringe on the RAMBUS

patent, and for that we will have to obtain the

views and interpretations of experts.” (RX 406

at 4; see also RX 416A at 1).

213. An August 16, 1993 Mitsubishi docu-

ment again raised the issue of whether Ram-

bus could have claims on features separate

479a

from any particular bus architecture. (RX 419A

at 1).

214. A January 11, 1996 memorandum indi-

cates that Mitsubishi subsequently conducted

an “investigation of the US patents owned by

Rambus” that were granted by the end of

October 1995 and that eighteen patents met

that criteria. (RX 528A at 1).

215. Mitsubishi also maintained a chart

tracking all of Rambus’s issued U.S. patents.

For example, one version of this chart begins

with Rambus’s first issued U.S. Patent No.

5,243,703, at number one and concludes with

U.S. Patent No. 5,578,940 which issued on

November 26, 1996 at number twenty-seven. —

(RX 2216 at 2, 4). Rambus’s ‘3827 patent is

listed at number twenty-three on the chart.

(RX 2216 at 3).

216. A later version of the Mitsubishi chart

contains thirty-seven Rambus patents and in-

cludes patents that issued in early 1998. (RX

2218 at 3-6).

217. A Mitsubishi analysis of the claims of

the PCT application specifically calls out the

modifiable access time register and notes its

similarity to SDRAM latency control. (RX

2213A at 27).

218. An August 24, 1996 report on a Rambus

meeting states: “Rambus’ patents. Issued: 16,

filed: 80. For example, data is transferred at

both edges.” (RX 756A at 1).

219. As Complaint Counsel concede, Rambus

has obtained patent claims that cover pro-

Hil.

480a

grammable CAS latency, variable burst length,

dual-edge clocking, and on-chip DLL as those

features are used in SDRAMs and/or DDR

SDRAMs. (Complaint, 7 91). Rambus has as-

serted claims covering these four features

against SDRAMs and DDR SDRAMs. (Com-

plaint, J 92).

JEDEC IS A COLLABORATIVE STAN-

DARD SETTING BODY FOR THE SEMI-

CONDUCTOR INDUSTRY

A. Early History of JEDEC

220. JEDEC was founded in 1958 and

originally named the “Joint Electron Device

Engineering Council.” (CX 302 at 10; J. Kelly,

Tr. 1773-74 (““JEDEC has been active within

an EIA organization under the name JEDEC

since approximately 1958, and under other

names with slightly different functions for a

number of years prior to that, probably dating

back to the 1940s.”)).

221. The current name of JEDEC is the

“JEDEC Solid State Technology Association.”

(J. Kelly, Tr. 1750-51).

222. Between 1991 and 1996, JEDEC was an

activity within the Electronic Industries Asso-

ciation (“EIA”) Solid State Products Division,

which was itself a division of the EIA’s Com-

ponents Group. (CX 3092 at 14, 27; J. Kelly,

Tr. 2075).

223. EIA is a “broad-based association that

represents the electronics industry in the

United States, and it engages in a variety of

48la

different activities in support of that industry.”

(J. Kelly, Tr. 1750; CX 302 at 28).

224. In 1998, EIA changed its name to the

Electronic Industries Alliance and JEDEC

became a separate division of EIA. (CX 302

at 11). In 1999, JEDEC became independently

incorporated. (CX 302 at 11).

225. Both EIA and JEDEC are headquar-

tered in Arlington, Virginia. (J. Kelly, Tr.

1751).

B. The Purpose and Function of JEDEC

226. JEDEC seeks to create consensus based

standards which reflect the interests of DRAM

manufacturers and exists because of an in-

dustry need for standardization. (CX 2767 at 1;

J. Kelly, Tr. 1784; Landgraf, Tr. 1685).

C. The Organization of JEDEC

1. Member Companies

227. A company becomes a member of both

JEDEC and EIA by completing and submitting

an application and paying dues. (CX 601; J.

Kelly, Tr. 1801-02; Rhoden, Tr. 294-95). “Elig-

ible organizations can become members of

JEDEC by joining the EIA Solid State Prod-

ucts Division or by joining JEDEC directly,”

and paying annual dues. (CX 208 at 7).

228. During the time Rambus was a JEDEC

member, dues were paid to EIA. (CX 602 at

6, 7).

229. There was no contractual relationship

between JEDEC and Rambus. (J. Kelly, Tr.

2075).

482a

230. During the i990’s, JEDEC had approx-

imately two hundred fifty member companies

who sent approximately 1800 individuals to

participate in approximately fifty committees.

(J. Kelly, Tr. 1774-75).

231. In 1992, when Rambus joined JEDEC,

the membership application stated that:

“JEDEC Committee membership is limited to

companies and independent entities of com-

panies that (1) manufacture solid state prod-

ucts, or provide related services or equipment,

and (2) participate in the United States mar-

ket.” (CX 602 at 2).

232. JEDEC’s membership includes com-

panies from around the world. (Rhoden, Tr.

294 (noting companies from Korea, Germany,

Taiwan and Japan); see CX 302 at 8).

233. Membership entitles companies to

attend meetings, receive minutes, vote, and

receive copies of standards and other pub-

lications. (J. Kelly, Tr. 1805-06).

234. Companies not interested in the out-

come of a particular issue were encouraged to

abstain from voting. (Rhoden, Tr. 303-04).

235. During the early and _ mid-1990’s,

JEDEC minutes were regularly circulated to

all members. (Crisp, Tr. 3139). The minutes

were also available in the early 1990’s to non-

members, with the possible exception of a Rus-

sian company. (G. Kelley, Tr. 2622-23).

236. JEDEC manual 21-H gives committee

chairs discretion to allow guests to attend

meetings: “faJll JEDEC Committee meetings

483a

are open to members, their designated alter-

natives, and guests invited by the Committee.

Others may attend meetings only with prior

approval of the Chairman.” (RX 1211 at 10).

2. The JEDEC Council, Board of Direc-

tors and Officers

237. Today, the JEDEC Board of Directors is

the governing body of JEDEC. (J. Kelly, Tr.

1768; CX 214 at 1, 14). Prior to 1999, the

JEDEC Council was the governing body of

JEDEC. (J. Kelly, Tr. 1768).

238. Prior to 1998, the JEDEC Council could

not unilaterally set or change policies without

approval of the EIA Engineering Department

Executive Council (““EDEC”). (See J. Kelly, Tr.

2078, 2105).

239. The chairman of the board of directors

is elected by JEDEC members. (Rhoden, Tr.

286).

240. The JEDEC chairman is responsible for

“the business aspect of JEDEC, trying to make

sure that we [JEDEC] have office space, staff,

relationships with other organizations, and to

make sure that we take care of the business

aspects of the corporation itself.” (Rhoden, Tr.

286-87).

241. Desi Rhoden is the current Chairman of

the JEDEC Board of Directors. (Rhoden, Tr.

283).

242. John Kelly is the current President of

JEDEC. (J. Kelly, Tr. 1750-51).

243. John Kelly has also been the General

Counsel of EIA since 1990. (J. Kelly, Tr. 1754).

484a

244. The EIA General Counsel is “the legal

counsel for all of the operating units within

BIA, including JEDEC” (J. Kelly, Tr. 1754).

The EIA General Counsel is the person re-

sponsible for interpreting EIA rules and the

JEDEC rules, including the JEDEC patent

policy. (J. Kelly, Tr. 1939; Sussman, Tr. 1348-

49).

245. While the General Counsel may inter-

pret the policies and rules, EDEC establishes

what the policies and rules are. (J. Kelly, Tr.

2078).

246. Today, JEDEC employs a staff of ten

persons to facilitate the meetings of JEDEC

committees. (J. Kelly, Tr. 1792-93). During the

early to mid-1990’s, the size of JEDEC’s staff

was considerably smaller than the current

size. (J. Kelly, Tr. 1795).

3. The JC 42 Committee

247. JEDEC is organized into committees

and subcommittees. (Landgraf, Tr. 1687).

248. The members of each committee or

subcommittee elect a chairman. (J. Kelly, Tr.

1794).

249. The JC 42 committee is concerned with

developing standards for memory products.

The JC 42 membership consists of “[a]lmost all

of the DRAM memory companies, SRAM mem-

ory companies, logic companies, customers of

memory, as well as interconnect companies,

such as socket manufacturers,” and testing

companies. (Williams, Tr. 765-66; Rhoden, Tr.

288).

485a

250. The JC 42 Chairman is responsible for

coordinating all the activities in the JC 42

committee and subcommittees, including the

scheduling of meetings. (Rhoden, Tr. 288).

251. The JC 42 committee had several sub-

committees focusing on particular specialized

subject matters. (J. Kelly, Tr. 1769; Rhoden,

Tr. 285 (JC 42 included subcommittees devoted

to DRAM (42.3), SRAM (42.2), memory mod-

ules (42.5), flash memory and other types of

programmable devices)).

252. JEDEC’s JC 42.3 subcommittee devel-

ops standards relating to DRAM products.

(Peisl, Tr. 4381; Rhoden, Tr. 283-84).

253. In late 1991, approximately forty to fifty

companies were represented on the JC 42.3

subcommittee. (Rhoden, Tr. 340-41; JX 10 at

1-2).

254. The JC 42 committee and its related

subcommittees typically meet between four

and eight times per year. (Rhoden, Tr. 340).

255. Minutes of JC 42 committee and its

subcommittees are prepared by Ken McGhee, a

staff person. (Rhoden, Tr. 327). There is a

review process that goes on before the minutes

are made official and distributed to members.

(Rhoden, Tr. 591).

256. The minutes of JC 42 and its sub-

committees record the key decisions that are

made during the standard development proc-

ess, including motions and votes. (Rhoden, Tr.

327-28). The minutes were intended to be a

chronological statement of the events and

486a

occurrences in the meeting, although they

were not a transcript. (Rhoden, Tr. 590-91).

D. The Standard Development Process

257. The standard development process be-

gins with discussions among the participants

at a JEDEC meeting -oncerning subjects that

members may feel should be considered as

possible standards. (Rhoden, Tr. 406-07).

258. JEDEC entertains a number of pro-

posals by members when working toward a

standard for a new device. (Rhoden, Tr. 415).

259. JEDEC members decide which of these

ideas to pursue. (Rhoden, Tr. 415-416).

260. There is a first showing or first pres-

entation when proposals typically receive an

item number. (Calvin, Tr. 1025).

261. In some cases, discussions of possible

features generate a survey ballot that requests

the members to give their views concerning

different solutions. (Rhoden, Tr. 481, 516).

262. Following the conclusion of the second

or subsequent presentations, the committee

decides if it wants to create a ballot to vote on

the substance of a proposed standard. (Rhoden,

Tr. 406-07).

263. JEDEC participants often had signifi-

cant differences of opinion concerning the

development of a standard. These differences

of opinion drove heated debates concerning the

merits of the various solutions to the technical

challenges facing the JEDEC participants.

(E.g., CX 711 at 14; CX 711 at 33; CX 711 at

47; CX 680 at 1; CX 680 at 2; Rhoden, Tr. 434-

487a

35 (“if you give ten engineers a problem, you'll

probably get 12 or 14 solutions, and the same

is true inside the discussions inside the com-

mittee”)).

264. From time to time, ballots failed or were

put on hold in the JEDEC committees because

the committees did not reach a consensus. (JX

12 at 6, 12; JX 19 at 10; JX 26 at 5).

265. If it preferred, a committee could pass

items individually but place the individual

items on hold until an entire list of related

items that were needed to define a single

standard was complete, and once that group of

ballots wes complete and passed, then together

the committee could motion them to go to

Council for publication. (G. Kelley, Tr. 2554).

266. After a JEDEC committee approves a

standard, the proposed standard is sent by a

ballot to the JEDEC board of directors, which

then has to again by a consensus approve the

ballot in order for the proposal to become a

JEDEC standard. (J. Kelly, Tr. 1785; Rhoden,

Tr. 406-07).

267. JEDEC’s consensus based _ process

means that the board of directors will consider

any committee votes that were cast in

opposition to the proposed standard. (J. Kelly,

Tr. 1786).

268. JEDEC’s consensus based process often

requires years in order to adopt a new stand-

ard or change an existing standard. (Polzin,

Tr. 3977; Peisl, Tr. 4453 (“JEDEC is tra-

ditionally a very slowly moving consortium,

and there’s a reason for that, because there’s

488a

sO many companies involved, it’s basically the

whole industry that produces parts for the PC

and the laptop and the server business, so to

try to reach consensus at JEDEC, based on my

experience, have been incredibly hard and

tough. In the last decade, essentially there

were only two standards that emerged for SDR

and DDR.”)).

269. In order to create common parts that

are plug compatible during the 1990’s, JEDEC

standards became more detailed. (CX 35 at 14-

15; G. Kelley, Tr. 2390).

270. Formal standardization in the DRAM

industry benefits the entire industry. (Prince,

Tr. 9016-17).

271. JEDEC standards are very valuable to

manufacturers. (CX 707 at 1 (“JEDEC is a big

deal to them [Samsung] because it [JEDEC]

represents the big users.”); Peisl, Tr. 4383-84;

Bechtelsheim, Tr. 5790).

E. Rambus’s Involvement in JEDEC

1.Rambus’s Participation in JEDEC

272. The first Rambus employee to attend a

JEDEC mecting on behalf of the company was

William Garrett, who first attended a meeting

in early December 1991 at the invitation of

Toshiba. (CX 670 at 1). Garrett was later

replaced as the Rambus primary represen-

tative at the JC 42.3 Committee by Richard

Crisp, who then became Rambus’s represen-

tative at JEDEC. (Crisp, Tr. 2929).

273. In February 1994 Rambus renewed its

JEDEC membership for the 1994 calendar

489a

year and in April 1995 Rambus paid its dues to

renew its JEDEC membership for the 1995

calendar year. (CX 602 at 6-7).

274. The final JEDEC meeting attended by

Rambus was the meeting in December 1995.

(CX 2104 at 853-54 (Crisp, Micron Dep.)).

Rambus did not renew its membership for

1996. (CX 887).

2.Rambus Representatives Learn

About the EIA/JEDEC Patent

Policy

275. Jim Townsend, JC 42 Chairman and

IBM representative, made a presentation con-

cerning the patent policy and showed the

patent tracking list at most JEDEC meetings

attended by Crisp. (JX 12 at 5, 28-29; JX 13 at

4; CX 42A at 2; JX 15 at 4; JX 16 at 5; JX 17 at

3; JX 18 at 3, 15-18; JX 19 at 4; JX 20 at 4, 15-

18; JX 21 at 4, 14-18; JX 22 at 3, 12-16; JX 25

at 3, 18-26; CX 88A at 2; JX 27 at 4, 20-25).

276. At the May 1992 JEDEC meeting,

Chairman Townsend showed a copy of the

new American National Standards Institute

(“ANSI”) patent policy implementation guide

and secretary Ken McGhee spoke concerning

the EIA patent policies. (CX 34 at 3, 10-11; CX

34A at 2, 7).

277. At the September 1993 JEDEC meet-

ing, Townsend showed a draft of portions of

the revised JEP 21-I Manual. (JX 17 at 12; see

also CX 2092 at 63-64 (Crisp, Infineon Trial

Tr.)). The draft stated only that “the committee

Chairperson must have received written notice

from the patent holder” that the license would

490a

be made available on a reasonable and non-

discriminatory basis. (JX 17 at 12). The draft

did not impose an obligation to disclose intel-

lectual property and did not advise the Chair-

person to call attention to such an obligation.

(JX 17 at 12).

3. Rambus Continued to Stay Abreast

of JEDEC and SyncLink Activities

278. The minutes of JC 42.3 meetings are

publicly available. (G. Kelley, Tr. 2623).

279. Several sources provided information to

Rambus about JEDEC meetings after Rambus

withdrew from JEDEC. (Crisp, Tr. 3413).

280. In 1997, Richard Crisp, Rambus’s prin-

cipal JEDEC representative, received informa-

tion about JEDEC’s activities from a source

called “deep throat.” (Crisp, Tr. 3414; CX 929

at 1; CX 932 at 1 (Crisp June 1997 email: “My

‘deep throat’ (DT) source told me that the DDR

bandwagon is moving fast within JEDEC with

all companies participating.”)).

281. Crisp also received unsolicited infor-

mation relating to proceedings at JEDEC from

an anonymous source called “Mixmaster,” a

reporter Crisp called the “Carroll contact,” and

a source known as “Secret Squirrel.” (Crisp, Tr.

3414-17; CX 935 at 1).

282. Crisp shared JEDEC-related informa-

tion he received from Deep Throat, the Carroll

Contact, Mixmaster, and other sources with

Rambus executives and engineers. (Crisp, Tr.

3413-17; CX 935 at 1; CX 929 at 1; CX 973 at

1; CX 979 at 1; CX 1014 at 1).

49la

283. After June 1996, Rambus continued to

follow SyncLink’s activities. (Crisp, Tr. 3388-

89; Crisp, Tr. 3395-96; CX 711 at 183).

EARLY DEVELOPMENT AND ADOPTION

OF JEDEC DRAM STANDARDS

A. The Initial SDRAM Standard

1. Demand for a New Generation of

Memory

284. “Asynchronous DRAM” is a term that is

used to describe DRAMs that are driven off the

row address strobe (“RAS”) and column ad-

dress strobe (“CAS”) signals where the RAS

and CAS actually control the operation of the

DRAM rather than a clock. (Jacob, Tr. 5394).

285. Page mode and extended data out

(“EDO” DRAMs) are types of asynchronous

DRAM. (Sussman, Tr. 1469; Polzin, Tr. 4031).

In the late 1980’s page mode and EDO DRAMs

were commonly used in the industry. (Suss-

man, Tr. 1361). Page mode and EDO DRAMs

were standardized at JEDEC. (Sussman, Tr.

1362; Prince, Tr. 9020-21).

286. In order to respond to the fising

demand for performance and to ensure that

the new JEDEC standard would result in

common parts that were plug compatible, the

JC 42.3 subcommittee began to standardize

certain aspects of DRAM performance and

design relationships. (CX 35 at 14; G. Kelley,

Tr. 2388-91). Prior to that time, JC 42.3 work

had generally focused on standardizing the

location of pins, also known as pin-out dia-

grams. (G. Kelley, Tr. 2388).

492a

287. The JC 42.3 subcommittee subsequently

exceeded those boundaries and began stand-

ardizing certain technologies that are unre-

lated to interoperability. An on-chip DLL, for

example, as included in the DDR SDRAM

standard is not required for interoperability.

Rather, as Complaint Counsel’s technical ex-

pert, Professor Jacob, explained, the DLL used

in DDR SDRAMs is transparent to the DRAM

interface. (Jacob, Tr. 5617-18).

288. A new generation of memory was

needed because the industry anticipated that

microprocessor and computer speeds would

increase and the industry demanded memory

that could operate at the same speeds. (CX

2088 at 291-92 (Meyer, Infineon Trial Tr.)).

289. One option considered by the JC 42.3

subcommittee was to continue to develop a new

generation of EDO DRAMs. (CX 711 at 1).

290. Subsequently, “Burst EDO” was also

developed and standardized at JEDEC in mid-

1995. (Williams, Tr. 873, 879-80; RX 585 at 1).

291. Burst EDO failed in the marketplace in

competition with SDRAM. (Williams, Tr. 829).

As Dr. Oh of Hyundai Electronics Industries

Co., Ltd. (“Hyundai”) testified regarding Burst

EDO: “this is enhanced version of EDO, and

we wanted to convince our customers the

advantages of this part, but was not accepted

by our customers.” (CX 2108 at 236 (Oh Dep.)).

292. JEDEC also began to consider a DRAM

that had been developed by IBM called “High

Speed Toggle.” (G. Kelley, Tr. 2584-85). High

493a

speed toggle is also known as “HST.” (G.

Kelley, Tr. 2441).

293. According to the definition provided by

Complaint Counsel’s expert, HST was an

asynchronous part. Professor Jacob testified

that an asynchronous DRAM is one where

asynchronous RAS and CAS signals control the

operation of the DRAM rather than a clock.

(Jacob, Tr. 5394). Since RAS and CAS were

asynchronous in HST, it follows from Professor

Jacob’s definition that HST was asynchronous.

(Rhoden, Tr. 568; Kellogg, Tr. 5173). Indeed,

a January 1992 documer’ written by Willi

Meyer of Siemens states: “IBM presented gen-

eric high speed toggle mode in Sep ‘90 which

was asynchronous.” (CX 2431 at 1; Kellogg, Tr.

5173).

294. In HST, IBM proposed to transfer data

on both edges of the toggle signal. (Kellogg, Tr.

5173; Sussman, Tr. 1381; Rhoden, Tr. 436-37;

CX 2080 at 242 (Karp, Micron Dep.)). While

some witnesses loosely referred to this toggle

signal as a “clock,” it was not a free running

clock like the system clock in a synchronous

memory such as SDRAM or DDR SDRAM.

(Rhoden, Tr. 437; Sussman, Tr. 1471).

295. IBM and Siemens made HST presen-

tations at JEDEC during 1990 and 1991 which

were included in survey ballots. (JX 2 at 92; JX

3 at 56-57; JX 3 at 7; CX 316 at 1; CX 314).

296. At the May 9, 1991 JC 42.3 meeting, the

subcommittee passed a motion to ballot the

IBM HST presentation. (JX 5 at 12). At the

same meeting Siemens also made a HST pres-

494a

entation that was like the IBM HST except it

used a G/pin instead of a new toggle pin. (JX 5

at 12).

2.Proposal of a Fully Synchronous

DRAM

297. At the JEDEC JC 42.3 meeting in May

1991, Howard Sussman of NEC proposed a

fully synchronous DRAM to JEDEC for the

first time. (Sussman, Tr. 1364; CX 2088 at 272-

75 (Meyer, Infineon Trial Tr.)).

298. It is unclear whether Sussman proposed

during his initial proposal to use a single edge

clock to input and output data and a pro-

grammable mode register to set CAS latency

and burst length. (Sussman, Tr. 1365-67 and

1373-75). There was no documentation about

the NEC proposal attached to the May 1991

minutes. (See JX 5).

299. In 1991, Sussman held an unofficial

meeting of JEDEC members in Boxborough,

Massachusetts to discuss his synchronous

DRAM proposal. (Sussman, Tr. 1369-70; CX

20). A report about that meeting prepared by

Sussman was intended to provide “a consensus

of where we were.” (Sussman, Tr. 1370). The

description of the features of Sussman’s

synchronous DRAM proposal does not include

any mention of a mode register, programmable

CAS latency, or programmable burst length.

(CX 20 at 1). A report about the Boxborough

meeting prepared by Gordon Kelley of IBM

makes clear that Sussman was proposing a

fixed CAS latency at this time. (RX 173 at 3).

Kelley’s list of the main features of the NEC

495a

proposal makes no mention of a mode register

or programmable burst length. (See RX 173

at 3).

300. At the JC 42.3 meeting on September

18, 1991, the subcommittee voted in favor of

the IBM HST technology. There were four no

votes and a number of comments. (JX 7 at 8).

NEC and Samsung commented that the use of

a separate toggle signal can limit speed. (JX 7

at 8). The subcommittee decided to put the

ballot on hold until more resolution to the

comments could be made. (JX 7 at 9).

301. Also at the JC 42.3 meeting on Sep-

tember 18, 1991, Sussman made a second pres-

entation of NEC’s SDRAM proposal. (JX 7 at

13 and 160-62; CX 2088 at 276 (Meyer, In-

fineon Trial Tr.)).

302. A number of other companies also pre-

sented synchronous DRAM proposals at this

meeting, including Texas Instruments, Tos-

hiba, and Hewlett-Packard. (JX 7 at 13, 163-

77).

303. At the September 1991 JEDEC meet-

ing, NEC’s second showing of the synchronous

DRAM proposal does not mention a mode reg-

ister, programmable CAS latency, or program-

able burst length. (JX 7 at 160-62).

304. It was not until October 1991, at a

second unofficial meeting of JEDEC members

in Portland, Oregon, that Sussman’s presen-

tation materials indicated that latency and

burst length should be programmable. Both

programmable CAS latency and programmable

burst length are included in a list of key

496a

features of the proposed device. (JX 10 at 50;

Sussman, Tr. 1373-75). A timing diagram, a

version of which had been used by Sussman at

the August 1991 non-JEDEC meeting as well

as the September 1991 JEDEC meeting, had

the following language added to the right-hand

column when it was used at the non-JEDEC

meeting in October 1991: “Latency is program-

mable.” (Compare JX 10 at 51 with CX 20 at 3

and with JX 7 at 160).

305. Toshiba also made a presentation for a

synchronous DRAM including programmable

CAS latency (JX 10 at 67), causing Howard

Kalter of IBM to remark that “programmable

latency was the cleverest item Toshiba ever

created.” (RX 199 at 2). By this time, Toshiba

was a Rambus licensee and was working on

the design of the first RDRAM chip. (Horowitz,

Tr. 8548-49).

306. At the JEDEC JC 42.3 meeting on

December 4-5, 1991 (the first JEDEC meeting

attended by Rambus), Mark Kellogg of IBM

made a presentation comparing HST to syn-

chronous DRAMs. (JX 10 at 5 and 84; Kellogg,

Tr. 5172-73).

307. Also at the JC 42.3 meeting of Decem-

ber 4-5, 1991, Howard Sussman presented the

results of a non-JEDEC meeting that had been

held in Portland, Oregon on October 24, 1991

to discuss high bandwidth DRAM. (JX 10 at 4;

Sussman, Tr. 1373). The conclusion from that

meeting was that a fully synchronous DRAM

with all signals referenced to a single positive

clock edge would best meet system require-

ments. (JX 10 at 50).

497a

308. At the JC 42.3 meeting held on Feb-

ruary 27-28, 1992, NEC, Hitachi, Fujitsu,

Toshiba, Mitsubishi and Sun all made presen-

tations regarding synchronous DRAM devices.

(JX 12 at 39, 42, 60, 69, 76, 94, 110).

309. These companies continued to also

make presentations regarding asynchronous

DRAMs that they proposed to develop as well.

For example, at the February 1992 JC 42.3

meeting, Toshiba made two presentations

regarding “address compression” for asynchro-

nous DRAMs, Fujitsu made a presentation

regarding an asynchronous DRAM in a new

kind of packaging, and NEC made a presen-

tation regarding an asynchronous DRAM with

a “revolutionary pinout.” (JX 12 at 11).

310. No further action on HST was taken at

the February 1992 JC 42.3 meeting. High

Speed Toggle items continued to be listed,

however, on an active items list presented at

the February 1992 meeting by the Subcom-

mittee Chairman. (JX 12 at 19; JX 12 at 20).

311. At a DRAM Task Group meeting on

April 9-10, 1992, NEC, Fujitsu, Toshiba,

Samsung, Hitachi and Mitsubishi presented

proposals for a fully synchronous DRAM. (CX

34 at 30, 33-36).

312. At the April 1992 DRAM Task Group

meeting, IBM proposed a slightly modified

version of its HST technology. (CX 34 at 32;

Kellogg, Tr. 5175).

313. Following the April 1992 DRAM Task

Group meeting, the JC 42.3 *subcom-

mittee decided to pursue a fully synchronous

498a

DRAM rather than IBM’s toggle mode. (G.

Kelley, Tr. 2515). The JC 42.3 subcommittee

also continued to develop various asynchro-

nous DRAMs while it was standardizing

synchronous DRAMs.

314. By the time Rambus attended its first

JEDEC meeting in December 1991, Howard

Sussman was reporting the consensus that a

“fully synchronous DRAM with all signals

referenced to a single (positive) clock edge

would best meet system requirements.” (JX 10

at 50).

315. The only evidence of consideration of

dual-edge clocking that Complaint Counsel

presented after this time is HST which actu-

ally proposed an asynchronous DRAM with

output data on both edges of a “toggle signal.”

(See CX 2431 at 1; Kellogg, Tr. 5173).

3. Inclusion of Programmable CAS

Latency and Burst Length

316. At the JC 42.3 meeting of December 4-

5, 1991, NEC presented the results of a

separate meeting in Portland, concluding that

the latency of data to the clock and the burst

length should be programmable. (JX 10 at 50).

317. At the same meeting, Texas Instru-

ments made a revised presentation of its

SDRAM proposal that also included _pro-

grammable CAS latency and programmable

burst length. (JX 10 at 4, 56; Rhoden, Tr. 419-

20).

318. Toshiba made a second showing that

included programmable CAS latency and burst

499a

length. (JX 10 at 67; Rhoden, Tr. 424). Wrap

length and burst length are the same thing.

(Rhoden, Tr. 419-20; Williams, Tr. 812-13;

Sussman, Tr. 1374-75). Neither of the ‘first

showings” at the September 1991 meeting

included programmable CAS latency and pro-

grammable burst length. (See JX 7 at 163-77).

319. The JC 42.3 Subcommittee considered a

number of alternative methods of determining

the CAS latency and burst length, including

using a fixed burst length, using pins to set the

CAS latency and burst length, and using fuses

to set CAS latency and bu™st length. (Rhoden,

Tr. 425-34; Kellogg, Tr. 5099-102 and 5130-31).

The alternative methods considered at JEDEC

were rejected. Complaint Counsel did not pre-

sent sufficient evidence to find that they ever

made it past the “first showing” stage. (See JX

10 at 5, 64, 71; Rhoden, Tr. 425-34; Kellogg, Tr.

5099-102).

320. At the December 1991 JC 42.3 meeting,

Samsung presented a proposal! for SDRAMs

that included fixed CAS latency and burst

length. Samsung proposed using a single CAS

latency of 2 and a single burst length of 8. (JX

10 at 71; Rhoden, Tr. 425-28; Kellogg, Tr.

5099-101). The Samsung proposal also in-

cluded a fuse option to select between two

different burst options. (JX 10 at 71; Rhoden,

Tr. 427-28).

321. At the December 1991 JC 42.3 meeting,

Mitsubishi presented a proposal for an

SDRAM that would use two pins, BT and WP,

to set the burst length and burst type. (JX 10

at 74; Kellogg, Tr. 5102). In its proposal,

500a

Mitsubishi provided for two burst length

options, a burst length of 4 and 8. (JX 1 at 74;

Rhoden, Tr. 430-34). The Mitsubishi presen-

tation was designated as a “first time presen-

tation.” (JX 10 at 5).

322. At the December 1991 JC 42.3 meeting,

Texas Instruments presented a proposal using

the WCBR cycle to program the mode register

to determine burst length and CAS latency.

(JX 10 at 50, 56).

323. WCBR indicates a situation where the

write signal is low and a CAS signal is sent

before the RAS signal. While common in a test

or refresh operation, CAS before RAS differs

from a normal read or write operation where

the RAS would be sent before the CAS.

(Kellogg, Tr. 5107-09).

324. At the JC 42.3 meeting of February 27-

28, 1992, NEC, Hitachi, Fujitsu, Toshiba and

Mitsubishi all made SDRAM proposals that

included programmable CAS latency and burst

length. (JX 12 at 39, 42, 60, 69, 76, 91, 94;

Sussman, Tr. 1382-83). At the same meeting,

Sun presented comments on what features it

would like to see included in SDRAMs, in-

cluding programmable CAS latency and burst

length. (JX 12 at 110).

325. At a DRAM Task Group meeting of

April 9-10, 1992, NEC, Fujitsu, Toshiba, Sam-

sung, Hitachi, Mitsubishi and IBM presented

proposals that included programmable burst

length. (CX 34 at 30, 32-35).

326. At the next meeting of JC 42.3 on May

7, 1992, the minutes of the April DRAM Task

50la

Group’s meeting were presented to the full JC

42.3 subcommittee. (CX 34 at 4 and 30-37).

327. At the May 1992 meeting of the JC 42.3

Subcommittee, Samsung, NEC, Toshiba, Hi-

tachi and Mitsubishi all made SDRAM presen-

tations that included programmable CAS

latency and burst length. (CX 34 at 44, 63, 83,

85, 99, 108, 140).

328. At the May 1992 JC 42.3 meeting, Cray

Corporation (“Cray”) gave a presentation that

proposed the use of fuses to select between a

set of features for a single bank configuration

and a set of featurers for a dual bank con-

figuration, where the feature set included,

inter alia, the CAS latency value and burst

length value. The Cray presentation was not

identified as a first showing in the minutes (see

CX 34 at 3-12), and there is no evidence that it

ever progressed to a first showing. (See Suss-

man, Tr. 1388; Kellogg, Tr. 5103-05).

329. On June 11, 1992, four SDRAM ballots

were sent out to all members. (CX 252A at 1).

One ballot sought approval for use of a

particular implementation of a mode register

which was used to program CAS latency and

burst length, as well as other features. (CX

252A at 1, 3; Crisp, Tr. 3075-76; Rhoden, Tr.

448; Williams, Tr. 811-12).

330. Richard Crisp was present at the July

1992 JC 42.3 meeting and participated for

Rambus in the discussion and the vote on the

proposals, including the mode register pro-

posal. (JX 13 at 1, 9-10). David Mooring of

Rambus also was present. (JX 13 at 2).

502a

Rambus voted “no” to the proposals. (JX 13 at

9-10; CX 2112 at 78-79 (Mooring, Dep.)).

Rambus’s comments cited technical reasons for

voting against it. (JX 13 at. 9-11). These were

the only votes cast by Rambus for or against

any JEDEC proposals.

331. The results of the vote on the mode

42.3 meeting on July 21, 1992. (JX 13 at 9-12;

Sussman, Tr. 1393). The initial tally showed

fourteen members in support of the proposal,

five against and seven abstentions. (JX 13 at

10). Various subcommittee members offered

comments, especially with respect to the need

for a CAS latency of 4. (JX 13 at 10-11).

Finally, it was agreed to re-ballot the mode

mode of 4. (JX 13 at 11).

332. At the September 16-17, 1992 JC 42.3

meeting, Sun made an SDRAM presentation

that included programmable CAS latency and

burst length. (CX 42 at 39-40).

333. On January 21, 1993, the DRAM Task

Group made minor technical edits to the NEC

mode register that included programmable

CAS latency and burst length and had pre-

viously been balloted as “Proposed Standard

for 16M Bit x 4 Sync DRAM Mode Register”

JC 42.3-92-85 (item 376.3). The DRAM Task

Group decided that a _ re-ballot was not

necessary and added the ballot to the pass-hold

category. (CX 47 at 3).

503a

4. Presentations of Additional

Technologies

a. Low Voltage Swing Signaling

334. During 1992, JEDEC work included a

number of presentations that included low

voltage swing signaling. At the February 27,

1992 JC 42.3 meeting, NEC, Fujitsu, Mosaid

Technologies Inc. (“Mosaid”), Sun and Intel all

made proposals that included low-voltage

swing signaling. (JX 12 at 39, 76, 104, 111,

113; Crisp, Tr. 3045-46). At this same meeting,

the JC 42.3 Committee discussed GTL tech-

nology for use with SDRAM. (JX 12 at 36, 56-

58, 60, 101-02, 104, 111).

335. At the April 8, 1992 Special SDRAM

Task Group meeting, the JC 42.3 Subcom-

mittee considered SDRAM proposals that in-

cluded low voltage swing signaling. (CX 34 at

32 (IBM), 33 (NEC, Fujitsu), 35 (Samsung,

Hitachi), 36 (Mitsubishi)).

336. At the May 7, 1992 JC 42.3 meeting, the

Subcommittee considered SDRAM proposals

that included low voltage swing signaling. (CX

34 at 59 (NEC), 122-123 (Fujitsu)).

337. At the September 16-17 1992, JC 42.3

meeting, the Subcommittee considered Sun’s

15 meg SDRAM specification which included

low voltage swing signaling. (CX 42 at 31).

338. Complaint Counsel did not present

evidence sufficient to find that these low

voltage swing signaling presentations were

ever balloted or that they were incorporated

into the SDRAM standard.

504a

b. Dual Bank Design

339. During 1992 and 1993, JEDEC work

included a number of presentations that in-

cluded dual bank design. At the February 1992

JC 42.3 meeting, the Subcommittee addressed

the topic of multiple active subarrays in two

presentations (JX 12 at 34, 37) and multibank

or dual bank design in other presentations.

(See, e.g., JX 12 at 60). The Subcommittee

considered proposals for multibank, or dual

bank, design from NEC, Mitsubishi, Fujitsu,

and Sun. (JX 12 at 39, 60, 76, 110).

340. At the May 7, 1992 JC 42.3 meeting, the

Subcommittee considered SDRAM proposals

that included dual bank design. (CX 34 at 59

(NEC), 122-123 (Fujitsu)).

341. During that meeting, Kelley of IBM,

prompted by Meyer of Siemens, asked Crisp

whether Rambus might have patent claims

that related to dual bank design. (CX 2089 at

i30, 133-37 (Meyer, Infineon Trial Tr.). “The

way how Mr. Kelley formulated the question

was: Do you want to give a comment on this?”

(CX 2089 at 136 (Meyer, Infineon Trial Tr.)).

Rambus declined to comment. (CX 2089 at 136

(Meyer, Infineon Trial Tr.)).

342. At the September 16-17 1992, JC 42.3

meeting, the Subcommittee considered Sun’s

15 meg SDRAM specification which included a

dual bank design. (CX 42 at 30 (“The 4M x 4

device is organized internally as two banks.”)).

343. Complaint Counsel did not present

evidence sufficient to find that these dual bank

design presentations were ever balloted or that

505a

they were incorporated into the SDRAM

standard.

c. Auto-Precharge

344, At a number of meetings during the

course of 1992, the JC 42.3 Subcommittee

discussed using the auto-precharge technology

in the SDRAM standard. (February 1992: JX

12 at 37, 39 (NEC), 76 (Fujitsu), 94 (Toshiba),

108 (Sun); April 1992: CX 34 at 32 (IBM), 33

(NEC), 35 (Hitachi); May 1992: CX 34 at 6,

150).

345. At the September 16-17, 1992 JC 42.3

meeting, the Subcommittee considered Sun’s

15 meg SDRAM specification which included

an “autoprecharge” option. (CX 42 at 45). Auto-

precharge was incorporated as a feature in the

JEDEC SDRAM 21-C standard, issued in

November 1993. (JX 56 at 115).

346. Complaint Counsel did not present

evidence sufficient to find that these auto

precharge presentations were ever balloted or

that they were incorporated into the SDRAM

standard.

d. Source Synchronous Clocking

347. At the April 1992 JC 42.3 Special Task

Group meet

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